Irma Esmer Papazian
San Carlos,CA
Summary
Award-winning Sr. Principal Engineer, an expert in server performance architecture and analysis, passionate about driving optimal performance on products, root-causing problems and improving execution efficiencies, and developing next set of technical leaders. After the lead architect role for the 3rd Gen Xeon CPU (Icelake-SP), played a pivotal role on each Xeon-CPU, stabilizing, enhancing power and performance (PnP) execution, optimizing performance and carrying learnings forward. Most recent achievements include defining targets and stretch goals that were inspiring to the extended teams, defining and driving additional PnP features during Si execution on 5th Gen Xeon (Emerald Rapids), and exceeding the performance efficiency commitments of the product.
Ready to pick up new technical leadership opportunities.
Overview
32
32
years of professional experience
Work History
Power and Performance (PnP) Lead Cross Data Center Products, Sr. Principal Engineer (Sr. PE)
Intel Corporation
10.2023 - Current
- Shepherds Xeon programs through their Si execution journey, brings architecture/micro architecture, workload and debug expertise to guide top PnP sightings to closure
- Ensures Si learnings including projection methodology updates are carried to next-generation product and partners
- Leads a multi-organizational AI LLM performance task force focused on characterizing and optimizing LLM workload performance on CPUs
Emerald Rapids (EMR) End-2-End PnP Lead, Sr. PE
Intel Corporation
09.2022 - 10.2023
- Formed alliances with extended validation organizations, developed new execution strategies focusing on automation and staged execution, while developing technical proficiency across the larger organization
- Drove several performance and power optimizations during Si execution, exceeding product performance efficiency commitments
- Received an Intel Achievement Award (IAA) for the significant contributions to EMR (aka. 5th Gen Xeon)
Sapphire Rapids (SPR) Performance Architecture Lead, Sr. PE
Intel Corporation
01.2021 - 01.2022
- Reorganized the performance architecture team, delivered clear KPI and targets to Si validation
- Provided leadership and direction to extended teams improving efficiency and output
- Ensured program milestones were met, specifically optimal performance was reached by PRQ deadline on broad workloads
Icelake Server Lead Architect + Performance Architecture Tech Leader, Sr. PE
Intel Corporation
01.2017 - 01.2021
- Became the lead architect for Icelake-SP, Intel’s first 10nm CPU, drove the product through multiple definitions due to timeline shifts
- Maintained the performance architecture technical leadership role for both 14nm and wave1 10nm Xeon servers
- Delivered Icelake-SP (April 2021, Cooper Lake-SP (June 2020), Cascade Lake-SP (April 2019)
Santa Clara Server Performance Architecture Team Leader
Intel Corporation
01.2010 - 01.2017
- Led the Santa Clara performance architecture team, growing team from 5 to 21 architects
- Oversaw performance modeling, architecture and projections for multiple products, significantly increasing the scope
- Delivered Ivybridge-EP/EX/EN in 2014 and Skylake-SP (Scalable Processor) in 2017
- Took on the lead SoC architect role for Cannon Lake-SP.
Nehalem-EX Performance Validation Lead, Principal Engineer (PE)
Intel Corporation
01.2007 - 01.2010
- Owned and led both pre- and post-Si performance validation for Nehalem-EX product
- Developed pre-Si test methodology and content for 2/4/8 socket system validation, delivering targeted performance at PRQ
- Received IAA for exceptional contributions on Nehalem-EX.
Sr. Performance Architect in Server Processor Architecture
Intel Corporation
01.2005 - 01.2007
- Spearheaded XPF (Merom/Penryn) core-based server product performance work, guiding architectural evaluations
- Developed a new SPEC CPU projection methodology, speeding up the multi-core simulations for homogenous workloads significantly, ~6x speedup for 8 core system evaluations
Processor Performance Architect in Itanium Processor Family (IPF) Architecture
Intel Corporation
04.1996 - 01.2004
- Modeled the micro-architecture for the memory hierarchy of the first IPF processor, codenamed Merced, in the cycle accurate simulation infrastructure
- Led a team of engineers developing performance models for next-generation IPF products
- Developed expertise in workload projections, both SPEC CPU and enterprise workloads.
Processor Architect in Intel Folsom Design Center
Intel Corporation
07.1992 - 04.1996
- Responsible for the system compatibility of Pentium-Pro based upgrade processors
- Completed a year-long Graduate Rotation Engineering program
Education
M.S. in Computer Engineering -
University of Wisconsin, Madison
05.1992
B.S. in Control and Computer Engineering -
Technical University of Istanbul, Turkey
06.1989
Skills
Authentic cross-organizational leader
- Fosters partnerships and collaboration
- Cultivates trust and continuous learning,
- demonstrates/instills accountability
- Passionate to deliver optimal product performance
- Spots and resolves communication problems
Mentorship, and technical leader/team development
Technical Expertise in
- Data center processor architecture and performance
- SoC architecture and end-2-end flows
- Pre- and post-Si performance models, analysis, debug, and validation
- KPIs, requirements, test specs
- Load-lines and power efficiency
- Workload characterization, optimization, and projections
- Data analysis and communications
Publications
- Intel Achievement Award, July 2024, “Emerald Rapids (EMR): Revitalizing the Intel brand”
- Intel newsroom article, Dec 13th, 2023, “Behind the builders: Discipline and Process Build Emerald Rapids”, https://www.intel.com/content/www/us/en/newsroom/news/discipline-process-built-emerald-rapids.html
- Tech Field Day, April 7th, 2021 “Architectural Deep Dive for 3rd Gen Intel Xeon Scalable Platform”
- Connected Social Media Podcast with Jake Smith, “How Intel Developed Its Latest Xeon Processors – Conversations in the Cloud – Episode 231”, https://connectedsocialmedia.com/19448/how-intel-developed-its-latest-xeon-processors-conversations-in-the-cloud-episode-231/
- HPC SC20, Nov 17th, 2020 “A Closer Look at Ice Lake Architecture”, https://sc20.gallery.video/detail/video/6208439527001/a-closer-look-at-ice-lake-architecture-overview
- Hot Chips 2020, Aug 17th, 2020, “Next Generation Intel Xeon(R) Scalable Server Processor: Icelake-SP”
- VentureBeat article on June 3rd, 2020, “Intel’s Irma Esmer Papazian: Building a career in tech and leading the Ice Lake-SP design team”, https://venturebeat.com/business/intels-irma-esmer-papazian-building-a-career-in-tech-and-leading-the-ice-lake-sp-design-team/
- Intel Architecture Day Dec 12th, 2018: ICX LCC Si Demo showcasing (1) VAES and VPCLMUL ISA and (2) IMDB ISA usage and speedups on ICX fist Si was still in PO.
- Hot Chips 2017, Co-Author: “The New Intel Xeon Scalable Processor (Formerly Skylake-SP)”
- IEEE Micro April 2015, Author “Ivy Bridge Server: A Converged Design”
- Hot Chips 2014, Author & Presenter “Ivybridge Server Architecture: A converged server”
- Intel Achievement Award, 2011, “Nehalem-EX: Unprecedented generational performance increase and design win backs in the enterprise server segment.”
- Modeling, Benchmarking and Simulation (MOBS) 2006, co-author, “FastMP: A Multi-core Simulation Methodology”
- Micro-35 2002, Finance Chair.
References
Available upon request
Timeline
Power and Performance (PnP) Lead Cross Data Center Products, Sr. Principal Engineer (Sr. PE)
Intel Corporation
10.2023 - Current
Emerald Rapids (EMR) End-2-End PnP Lead, Sr. PE
Intel Corporation
09.2022 - 10.2023
Sapphire Rapids (SPR) Performance Architecture Lead, Sr. PE
Intel Corporation
01.2021 - 01.2022
Icelake Server Lead Architect + Performance Architecture Tech Leader, Sr. PE
Intel Corporation
01.2017 - 01.2021
Santa Clara Server Performance Architecture Team Leader
Intel Corporation
01.2010 - 01.2017
Nehalem-EX Performance Validation Lead, Principal Engineer (PE)
Intel Corporation
01.2007 - 01.2010
Sr. Performance Architect in Server Processor Architecture
Intel Corporation
01.2005 - 01.2007
Processor Performance Architect in Itanium Processor Family (IPF) Architecture
Intel Corporation
04.1996 - 01.2004
Processor Architect in Intel Folsom Design Center
Intel Corporation
07.1992 - 04.1996
M.S. in Computer Engineering -
University of Wisconsin, Madison
B.S. in Control and Computer Engineering -
Technical University of Istanbul, Turkey
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