Isaac Nii Lante Bruce

Innovative analog design engineer with background in diverse engineering projects, including design optimization and chip verification. Strong analytical skills, adept at problem-solving and implementing efficient solutions to improve chip performance whiles minimizing power and area costs.

• Design of a Closed Loop Type III compensated Buck Converter, The buck converter was designed in the TSMC 180nm process. Efficiency of at least 85% was recorded at loads of 300mA, 500mA and 800mA. A worst-case ripple of 10mV was recorded.
• Design of a Low-Voltage RRIO Fully-Differential Two-Stage Operational Amplifier, The amplifier was designed in the TSMC 180nm process. The RR input stage was implemented using the Allen architecture while the output stage was implemented using the Monticelli architecture.
• Design of a 12-bit 5 Mega samples per second pipeline ADC, The pipeline ADC was designed in the TSMC 180nm process. Each stage of the pipeline ADC was a 1.5bit stage. A linearity of 11 bits was recorded.
• Design of a 1.8GHz RF Amplifier
• Design of a 6th Order Lowpass Butterworth OTA-C Filter, The filter was implemented using the leapfrog architecture with a 3dB frequency of 40MHz and a programmable band edge of ±10% around the nominal frequency. The trimmable cut-off frequency was implemented by tuning the gate voltages of the OTAs effectively changing the effective transconductance of each stage.
• Moving Average and Standard Deviation Circuit, A Verilog code was written and synthesized in the TSMC 180nm process to implement a moving average and a standard deviation circuit. The design was optimized for power and area.

• I. Bruce, P. O. Farayola, S. K. Chaganti, A. Sheikh, S. Ravi, D. Chen, An Ordinal Optimization-Based Approach To Die Distribution Estimation For Massive Multi-site Testing Validation: A Case Study, 2021 IEEE European Test Symposium (ETS), Bruges, Belgium, 2021, 1-4, 10.1109/ETS50041.2021.9465402
• I. Bruce, P. O. Farayola, S. K. Chaganti, A. Sheikh, S. Ravi, D. Chen, A Weighted-Bin Difference Method for Issue Site Identification in Analog and Mixed-Signal Multi-Site Testing, J. Electron. Test., 39, 1, 57–69, Feb, 2023, 10.1007/s10836-023-06047-w
• I. Bruce, M. Sekyere, E. N. Darko, E. O. Odion, K. Bhatheja, D. Chen, Small Area, High Accuracy Sub-Radix Resistive Current Mode Digital-To-Analog Converter with Novel Calibration Algorithm, 2023 IEEE 66th International Midwest Symposium on Circuits and Systems (MWSCAS), Tempe, AZ, USA, 2023, 477-481, 10.1109/MWSCAS57524.2023.10406103
• I. Bruce, E. N. Darko, E. O. Odion, M. Crabb, D. Chen, Redundancy based Resistor String DAC with an all-digital calibration algorithm., IEEE International Midwest Symposium on Circuits and Systems, Boston, 2024, accepted for publication
• I. Bruce, E. N. Darko, E. O. Odion, K. Bhatheja, M. Crabb, D. Chen, A 3-segment Interpolating String DAC with Low-Cost Built-In-Self-Test Capabilities., IEEE Computer Society Annual Symposium, Knoxville, 2024, accepted for publication
• E. O. Odion, I. Bruce, E. N. Darko, K. Bhatheja, M. Crabb, D. Chen, Ultra-Small Area, Highly Linear, Modified All Mosfet Digital-To-Analog Converters with Novel Real time Digital Calibration Algorithm., IEEE Computer Society Annual Symposium, Knoxville, 2024, accepted for publication
• M. Sekyere, I. Bruce, D. Chen, Matching Critical Analog Circuit Components Up To 3rd Order Gradients
• P. O. Farayola, I. Bruce, S. K. Chaganti, A. Sheikh, S. Ravi, D. Chen, Cross-Correlation Approach to Detecting Issue Test Sites in Massive Parallel Testing, 2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), Austin, TX, USA, 2022, 1-6, 10.1109/DFT56152.2022.9962367
• P. O. Farayola, I. Bruce, S. K. Chaganti, A. Sheikh, S. Ravi, D. Chen, Massive Multisite Variability-Aware Die Distribution Estimation for Analog/Mixed-Signal Circuits Test Validation, 2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), Montpellier, France, 2021, 1-6, 10.1109/DTIS53253.2021.9505144
• P. O. Farayola, I. Bruce, S. K. Chaganti, A. Sheikh, S. Ravi, D. Chen, Systematic Hardware Error Identification and Calibration for Massive Multisite Testing, 2021 IEEE International Test Conference (ITC), Anaheim, CA, USA, 2021, 304-308, 10.1109/ITC50571.2021.00042
• P. O. Farayola, I. Bruce, S. K. Chaganti, A. Sheikh, S. Ravi, D. Chen, The Least-Squares Approach to Systematic Error Identification and Calibration in Semiconductor Multisite Testing, 2022 IEEE 40th VLSI Test Symposium (VTS), San Diego, CA, USA, 2022, 1-7, 10.1109/VTS52500.2021.9794216
• P. O. Farayola, I. Bruce, S. K. Chaganti, A. Sheikh, S. Ravi, D. Chen, Optimal Order Polynomial Transformation for Calibrating Systematic Errors in Multisite Testing, 2022 IEEE International Test Conference (ITC), Anaheim, CA, USA, 2022, 509-513, 10.1109/ITC50671.2022.00062
• M. Sekyere, E. N. Darko, I. Bruce, E. O. Odion, K. Bhatheja, D. Chen, Ultra-Small Area, Highly Linear Sub-Radix R-2R Digital-To-Analog Converters with Novel Calibration Algorithm, 2023 IEEE 66th International Midwest Symposium on Circuits and Systems (MWSCAS), Tempe, AZ, USA, 2023, 604-608, 10.1109/MWSCAS57524.2023.10406079
• K. Bhatheja, S. Chaganti, J. Leisinger, E. N. Darko, I. Bruce, D. Chen, A BIST Approach to Approximate Co-Testing of Embedded Data Converters, IEEE Design & Test, 41, 3, 21-28, June, 2024, 10.1109/MDAT.2024.3365958

• Iowa State University/ Semiconductor Research Corporation (SRC), Worked with test engineers from Texas Instruments and Industry Liaisons from SRC to develop algorithms for issue site identification and calibration in the Multisite Testing Systems using statistical algorithms., Developed a hierarchical least squares decomposition algorithm to identify the systematic sources in variation in wafer level measurements obtained from a Multisite Testing Systems., Developed proprietary software programs for issue site identification and calibration in Multisite Testing systems for use by SRC and Texas Instruments., Proposed and designed multiple digital-to-analog converters (DAC) which take advantage of digital calibration to reduce design area while still maintaining high linearity., Fabricated proposed DAC architectures and developed measurement systems to test fabricated chips and validated proposed designs., Contributed significantly to the development of algorithms to generate layout patterns that cancel systematic gradient effects to guarantee matching in analog circuits layout., Began the development of an algorithm to determine the optimal placement of temperature sensors in semiconductor wafers for optimal recovery of on-chip thermal profiles., Developed and implemented a thermal profile estimation algorithm using Gaussian Process Regression.
• University of Notre Dame, Verified the validity of the compressed sensing theory in spectrum measurement and provided an analysis showing that the performance metric currently used may not always be accurate., Worked on a low-cost RF spectrum sensor, RadioHound, where I mainly focused on debugging existing errors in the python firmware.