Conducted unit tests to identify potential issues before releasing product updates.
Integrated existing software products into larger systems as needed.
Documented programming processes including coding logic, debugging steps and implementation details.
Collaborated with other developers on code reviews, design changes and application enhancements.
Optimized existing database queries for improved performance and scalability.
Developed, tested and implemented software programs to meet customer requirements.
Provided support for existing applications by troubleshooting bugs and implementing fixes.
Designed, coded and debugged applications, such as Qt GUIs in C++.
Senior Capstone Design
University of California Berkeley
Berkeley
08.2022 - 12.2022
Designed a 3-stage pipelined RISC-V CPU with a naive branch predictor, control and data hazard protocols, the Riscv151 memory architecture, and a UART for tethering
Used Verilog to implement CPU on the Xilinx PYNQ platform
Optimized CPU for performance and cost by maximizing the Iron Law and improving the FPGA's resource utilization.
Education
Bachelor of Science - Electrical Engineering and Computer Science
University of California Berkeley
Berkeley, CA
05.2023
Skills
Python
C
Java
Verilog
Interface design and implementation
Application debugging
Object-Oriented Programming
Testing and debugging
Network Security
Software Development
Software integration
System Design
Circuit boards
Circuit Design
Electrical circuitry knowledge
Languages
Spanish
Native/ Bilingual
English
Native/ Bilingual
Certification
Granted Secret Clearance along with CAC card
Timeline
Programmer II
JT4 LLC
11.2023 - Current
Senior Capstone Design
University of California Berkeley
08.2022 - 12.2022
Bachelor of Science - Electrical Engineering and Computer Science