JAYASHREE CHAVA
Manteca,California
Summary
Senior IC layout and mask designer specializing in full-chip, block-level, and custom physical design for analog, mixed-signal, and RF silicon. Work spans advanced FinFET and planar nodes, with hands-on DRC/LVS/ERC closure, floorplanning, ECO integration, and tape-out risk reduction using Synopsys-based flows, Cadence Virtuoso, Calibre, and IC Validator.
Overview
28
28
years of professional experience
Work History
Senior IC Layout / Mask Designer
INTEL CORPORATION
Santa Clara, California
09.1998 - Current
- Coral Rapids - Intel 14A | Xeon 8P Core Server Processor (Recent - 2026).
- Spearheaded initial planning and layout phases, covering 80% of North Block chip area and ensuring alignment with design specifications.
- Strategically planned and routed thousands of global high-speed routes, seamlessly managing Ultra Path Interconnect (UFI) and Mesh signals using customized internal design tools.
- Implemented full-chip routing across analog blocks by creating precise full-chip layouts, managing analog blockages, and executing UFI routing within standard Synopsys physical design environments.
- Diamond Rapids – Intel 18A-P | Xeon 7 Server Processor (2023 – 2025)
- Owned physical implementation from floorplan handoff through route completion and physical verification closure utilizing Synopsys-based internal flows, Cadence Virtuoso, and IC Validator.
- Partnered cross-functionally with design, timing, DFT, and verification teams to close critical implementation bottlenecks and alignment issues on advanced multi-patterning layers.
- Resolved congestion and pin-access closure issues near device boundaries across multiple layers, reducing tape-out delays and facilitating design convergence.
- Triaged early-stage finish designs and provided critical systematic feedback during Floorplan Mock (FP mock0) phases, identifying base layer DRC and construction problems for physical optimization (PO) resolution.
- Streamlined final layout verification clean-up with automated verification decks, reducing manual design verification overhead for downstream teams.
- Sierra Forest - Xeon Gen 6 Data center processor
- Optimized congestion, pin-access, and blockages to dramatically improve routability across Auto Place & Route (APR) designs.
- Skylake - 14nm | Gen 6 Core Processor.
- Led top-level and block-level layout integration for complex CPU/SoC programs, while managing hierarchical connectivity, pin propagation, and interface route closure across multiple partitions.
- Accelerated critical tape-out milestones by 60% by executing rapid manual ECOs for APR blocks and standardizing thorough documentation, preventing costly silicon re-spins.
- Resolved complex hierarchical LVS errors using Calibre and achieved route closure by mitigating noise, minimum, and maximum violations.
Education
Certification - CMOS Advanced Physical design /Layout Verification Training
San Jose City College
San Jose, CAB.S. - Mechanical Engineering
Nagpur University
Maharashtra, IndiaSkills
- EDA Tools & Flows: Synopsys-Based Internal Flows Cadence Virtuoso Calibre DRC/LVS Synopsys IC Validator Custom Compiler
- Layout Expertise: Full-Custom & Semi-Custom Layout Full-Chip & Block-Level Integration Hierarchical Routing Handoff Clock-Aware Routing & Congestion Closure Physical Design & Floorplanning: Power Planning Placement Optimization Pin-Access Resolution Analog Block Shielding & Placement Verification & Sign-off: DRC / LVS / ERC Closure Physical Verification Base Layer Design Rule Resolution Antennas & Electromigration (EM) Fixes Methodology & Automation: Tcl Scripting for Layout Checks/Debug Engineering Change Orders (ECO) Integration Tape-out Readiness Tracking & Risk Mitigation
Personal Information
- Title: SENIOR IC LAYOUT /MASK DESIGNER
- Work Permit: US Citizen
Timeline
Senior IC Layout / Mask Designer
INTEL CORPORATION
09.1998 - Current
Certification - CMOS Advanced Physical design /Layout Verification Training
San Jose City College
B.S. - Mechanical Engineering
Nagpur University