JEAN NDO

• FPGA Architecture & RTL Development

- Architect and implement FPGA-based Data Acquisition (DAQ) systems using VHDL and Verilog within the Xilinx Vivado and Vitis design flow.

- Develop scalable RTL modules targeting Xilinx 7-Series, UltraScale+, and Versal (HBM-enabled V80) platforms.

- Design high-throughput datapaths optimized for performance, latency, and resource utilization.

- Create and maintain XDC timing constraints; perform static timing analysis and achieve timing closure on high-frequency designs.

- Implement robust CDC (Clock Domain Crossing) strategies for multi-clock systems.

• High-Speed Interfaces & Networking

- Design and integrate high-speed serial interfaces using Xilinx Gigabit Transceivers (GTP, GTX, GTY, GTM).

- Implement Aurora-based communication links for low-latency data transfer.

- Develop and validate 10 Gigabit Ethernet solutions using Xilinx High-Speed Ethernet Subsystem IP.

- Integrate PCIe-based high-bandwidth data paths leveraging HBM memory architecture on Versal V80.

• DMA & High-Performance Data Movement

- Design and integrate AXI DMA and QDMA (Queue Direct Memory Access) IP cores for high-speed host-to-FPGA and FPGA-to-host data transfers.

- Configure and optimize AXI4 and AXI4-Stream interfaces for efficient packetized and memory-mapped transactions.

- Work with Linux-based QDMA drivers for PCIe communication, queue configuration, descriptor management, and performance tuning.

- Implement memory-mapped and streaming data paths ensuring compliance with 4KB boundary and AXI protocol requirements.

• Embedded Systems & Software Integration

- Define and implement memory map allocation for custom IP cores and device drivers, ensuring proper address decoding and system-level integration.

- Generate hardware platforms (.xsa files) from Vivado and import into Vitis for embedded software development.

- Develop embedded applications in C language, interfacing with AXI peripherals and DMA engines.

- Configure and manage bare-metal or Linux-based software stacks for FPGA acceleration systems.

- Perform hardware-software co-design, debugging system-level issues using ILA, driver logs, and software instrumentation.

• Verification & Validation

- Develop verification environments using OSVVM and GHDL for RTL simulation and functional validation.

- Create structured testbenches with constrained-random testing and coverage analysis.

- Perform post-synthesis and post-implementation validation to ensure design integrity.

• System Engineering & Collaboration

- Produce detailed design documentation including architecture diagrams, interface specifications, and integration guides.

- Participate in code reviews and design reviews to ensure adherence to engineering best practices.

- Collaborate cross-functionally with firmware, software, and system engineers to deliver integrated solutions.

. Contributed to the reduction of Maintenance cost by 20%
· Reading blueprints and electrical drawing for troubleshooting and analysis
· Recommended and initiated projects, preventing recurrence of Production issues and breakdowns