Summary
Overview
Work History
Education
Skills
Websites
Publications And Conference
Projects
Timeline
Generic
JEGADEESWARI ETHIRAJ

JEGADEESWARI ETHIRAJ

Phoenix,AZ

Summary

Business Intelligence Analyst with specialization in Microsoft Power BI and SQL programming. Demonstrated success in creating impactful dashboards that enhance data-driven decision-making. Strong expertise in digital electronics and VLSI design methodologies, providing solutions to complex challenges and generating actionable insights.

Overview

4
4
years of professional experience

Work History

A Complete Guide to Power BI Dashboard for Project

Udemy
05.2025 - Current

The Business Intelligence Analyst

Udemy
01.2025 - 06.2025

Microsoft Power BI Desktop for BI

Udemy
01.2025 - 06.2025

VLSI Design Methodologies

Maven Silicon VLSI Design and Training center
Bangalore, India
06.2022 - 06.2022

Advanced VLSI design and verification course

Maven Silicon VLSI Design and Training center
Bangalore, India
07.2021 - 06.2022

Education

Master of Engineering - Communication Systems

Anna University
Chennai, India
06-2015

Bachelor of Engineering - Electronics and Communication Engineering

Anna University
Chennai, India
06-2013

Skills

  • Microsoft Power BI
  • Dashboard development
  • SQL programming
  • Digital electronics
  • Verilog and System Verilog
  • UVM methodology
  • Team leadership
  • Problem solving

Publications And Conference

  • Design of Low Complexity Polar Coded Spatial Modulation, Middle-East Journal of Scientific Research, 23, 5, 981-986, 2015.
  • Performance analysis of Polar Coded Spatial Modulation for MIMO System
  • Study on Polar Coded Spatial Modulation for MIMO System
  • MIMO Wireless Communication and Future Networks

Projects

  • Designed a project for Maven Market with the entire business intelligence workflow: connecting and shaping the data, building a relational model, adding calculated - Udemy
  • Router 1x3 - RTL Design & Verification, Architected the top-level structure for the design and Implemented RTL using Verilog HDL., Design & Verification of each block i.e., 3 FIFOs, Synchronizer, Register & FSM using TestBench Stimulus., Generated Synthesis report (Code Coverage) of the top-level module.

Timeline

A Complete Guide to Power BI Dashboard for Project

Udemy
05.2025 - Current

The Business Intelligence Analyst

Udemy
01.2025 - 06.2025

Microsoft Power BI Desktop for BI

Udemy
01.2025 - 06.2025

VLSI Design Methodologies

Maven Silicon VLSI Design and Training center
06.2022 - 06.2022

Advanced VLSI design and verification course

Maven Silicon VLSI Design and Training center
07.2021 - 06.2022

Master of Engineering - Communication Systems

Anna University

Bachelor of Engineering - Electronics and Communication Engineering

Anna University