Summary
Overview
Work History
Education
Skills
Timeline
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Jie Huang

ASIC Design Verification Engineer
San Diego,CA

Summary

Detail-oriented, organized and meticulous employee. Works at fast pace to meet tight deadlines. Enthusiastic team player ready to contribute to company success.

Overview

6
6
years of post-secondary education

Work History

ASIC Engineer

Qualcomm Technologies Inc
4 2020
  • SoC performance verification
  • SoC performance verification test planning using Cadence PERSPEC tool, exercised performance of CPUSS, NOC and memory subsystem in Snapdragon premier tier SoC with solid understanding of ARM v8 architecture, ARM bus protocols, SoC architecture and verification environment.
  • Performed accurate measurement for system latency, ST/MT bandwidth, cache maintenance, MTE, DVM, atomics/exclusive, DRAM encryption and DMA performance.
  • Executed benchmarks such as Dhrystone, Linpack and Stream algorithm for CPUSS/NSP in SoC verification platform.
  • Debugged performance bottleneck with ARM pc tracer, bus monitor and waves, wrote python script to analyze simulation log.
  • Worked with subsystem teams and architects to resolves performance related architecture problems by applying sound ASIC engineering practices.
  • Accelerated performance platform for use case verification.
  • Built UVM environment which utilized emulation friendly QNS4 and AXI VIPs to replay system use case traces in SoC DV
  • Wrote UVM sequences that test structural latency and system bandwidth for multimedia system, GPU and PCIE
  • Collected bandwidth, transaction latency per priority level and DDR utilization data.
  • Verified key system use case KPI was met; reduced simulation time from 7 days to 2 hours using veloce accelerated platform.
  • SoC Power verification
  • Test development with Cadence PERSPEC, identified design bugs in SoC Always-on subsystem, temperature sensor controller and CPR controller in IoT chip using waveform and simulation logs.
  • Verified system user cases such as chip bring up, warm reset, subsystem collapse and SoC RBSC, identified dozens of critical system level bugs.
  • Improved team productivity by providing technical guidance and mentoring junior engineers

Debug Automation Tool

Qualcomm SOC design verification team
- 09.2019
  • Designed signal trackers to monitor frequency switch status and bus transactions of DDR controller.
  • Wrote python scripts to automate debugging based on output of trackers in DDR subsystem.
  • The tool helped save 15% simulation time and 20 mins debug time in average.

Graphics Accelerator in FPGA

- 05.2019
  • Implemented VGA module controller and framebuffer in SDRAM on FPGA board.
  • Designed and implemented 3D rendering pipeline in systemVerilog
  • Wrote device driver that ran in user space to control the graphics accelerator from microcontroller.

Hardware Accelerator for Convolution Neural Network vgg19

- 11.2018
  • Used SystemC to realize convolution algorithm and build CNN vgg19 in Stratus HLS
  • Built cache in accelerator to partially store input data, weights, and bias from main memory.
  • Implemented pingpong buffer in cache to overlap memory access and computation.

Video Image Acquisition System (VLSI) Design

- 08.2017
  • Self-taught Verilog programming language and learnt the use of Vivado integrated design environment.
  • Use Verilog to implemented driver for both the OV2640 camera and the LCD in FPGA
  • Initialized the LCD and camera using 80-system and i2C protocol respectively with Moore FSM
  • Controlled LCD and sequentially read in memory data by using frame synchronization signal (Vsync) and the line sync signal (HREF) from camera and eventually displayed image on LCD.

Education

M.S. in Electrical Engineering -

Columbia University
116th And Broadway, New York, NY 10027
07.2018 - 05.2019

B.S. in Electronic and Information Engineering (double degree) -

Tongji University
Shanghai, China
09.2014 - 07.2018

B.S. in Electronic and Information Engineering (double degree) -

Politecnico Di Torino
Turing, Italy
07.2017 - 07.2018

Skills

Verdi, Vcs, Perspec, Veloce, Vivado, Multisim, Spice, Matlab, Cadence, Stratus HLS

C/C, Python, Verilog/SystemVerilog, UVM, PSS

Timeline

M.S. in Electrical Engineering -

Columbia University
07.2018 - 05.2019

B.S. in Electronic and Information Engineering (double degree) -

Politecnico Di Torino
07.2017 - 07.2018

B.S. in Electronic and Information Engineering (double degree) -

Tongji University
09.2014 - 07.2018

ASIC Engineer

Qualcomm Technologies Inc
4 2020

Debug Automation Tool

Qualcomm SOC design verification team
- 09.2019

Graphics Accelerator in FPGA

- 05.2019

Hardware Accelerator for Convolution Neural Network vgg19

- 11.2018

Video Image Acquisition System (VLSI) Design

- 08.2017

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Jie HuangASIC Design Verification Engineer