Jing Liu
Nashua,NH
Summary
Accomplished Senior Digital Verification Engineer with a proven track record at Allegro MicroSystems LLC, specializing in ASIC design verification and robust DSP algorithm validation. Leveraged strong UVM, SystemVerilog knowledge, and exceptional problem-solving skills to mentor junior engineers and enhance team capabilities. Demonstrates a lifelong curiosity-driven learning approach, ensuring continuous improvement and innovation in high-stakes environments.
Overview
11
11
years of professional experience
Work History
Senior Digital Verification Engineer
Allegro MicroSystems LLC
06.2021 - Current
- Experienced in generating various real-scenario stimulus and assertion-based checkers to ensure the robustness of core DSP algorithm such as vibration immunity and jitter performance.
- Experienced in addressing the verification complexities of output protocols such as SENT, AK/PW.
- Experienced in performing a fault injection and analysis campaign for critical digital blocks to guarantee the design meets the specified ASIL grade.
- Experienced in evaluating formal verification tool(UNR) to enhance functional coverage closure.
- Mentored junior engineers in best practices for verification methodologies and coding guideline to improve team skillsets.
Digital Verification Engineer
Allegro MicroSystems LLC
03.2015 - 06.2021
- Collaboratively improve and maintain the EEPROM memory VIP to ensure its effectiveness across all business units
- Experienced in verifying serial communication protocols, including I2C, SPI and UART within power monitoring ICs.
- Experienced in developing PRNM models to verify the functionality of the top-level digital mixed-signal design.
- Experienced in verifying complex digital blocks such as access control, memory control, temperature compensation, watchdog, analog trimming, MUX, functional safety and DFT to ensure reliability in various automotive sensor applications(position, speed, transmission)
Analog/Mixed Signal Design Engineer
Broadcom
02.2014 - 11.2014
- Design and simulate the CMU block for high-speed IO(SerDes) and gain in-depth knowledge about PCIe protocol.
Education
Master of Science - Electrical Engineering
University of Minnesota-Twin Cities
Minneapolis, MN12-2013
Bachelor of Science - Electrical Engineering
University of Minnesota-Twin Cities
Minneapolis, MN05-2012
Skills
- Strong UVM, TLM, SystemVerilog and OOP knowledge
- Extensive experience of Cadence Xcelium, VManager and Simvision
- Strong debugging and problem-solving skill
- Strong communication skills
- Strong background in ASIC design verification flow
- Constraint Random and Assertion-based verification with coverage-driven mindset
- Working knowledge of script language such as Python, Perl and Makefile
- Familiarity of revision control tools like Cliosoft, Git
- Familiarity of gate level simulation and power analysis
- Good understanding of concepts in Analog design, VLSI design automation, computer architecture, parallel computing and computer graphics
- Quick and curiosity-driven lifelong learner
Timeline
Senior Digital Verification Engineer
Allegro MicroSystems LLC
06.2021 - Current
Digital Verification Engineer
Allegro MicroSystems LLC
03.2015 - 06.2021
Analog/Mixed Signal Design Engineer
Broadcom
02.2014 - 11.2014
Master of Science - Electrical Engineering
University of Minnesota-Twin Cities
Bachelor of Science - Electrical Engineering
University of Minnesota-Twin Cities
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