Summary
Overview
Work History
Education
Skills
Publications
Qualifications
Accomplishments
Timeline
Generic

Jinkyu Choi

Sammamish,WA

Summary

- Innovative RTL design Engineer with expertise in satellite communication system design and validation focused on digital beam-forming technologies. Proficient in Ka-band RF and high-speed gigabit transceiver protocols, leveraging Cortex-A53/A72 CPU architecture for enhanced performance. Achieved rapid DSP RTL prototyping through high-level model design, contributing to project efficiency and effectiveness. Aspires to further advance satellite communication capabilities through cutting-edge technologies.

- Validation system design for high speed analog-to-digital converter using JESD204 protocol and Cortex ARM based CPU architecture with the efficient memory interface
- Top design and verification Engineer with a success story in 802.11ah WiFi chip for the first time of the world. Offer excellence in validation and verification methodologies for Wifi PHY module and design technologies for high performance, also even low power.
- Lead to success about the camera image signal processing chip (DRIMe5) of Samsung mirror-less premium camera - NX1, verification of the whole chip as large as 150 million gate counts.

Overview

20
20
years of professional experience

Work History

Sr. FPGA Design Engineer

Amazon
Redmond, WA
06.2021 - Current
  • Cortex A72-based CPU system design with AXI peripherals on the petalinux.
  • Data flow control block design, including dispatcher and scheduler.
  • High-speed interface design with the Interlaken protocol.
  • DSP-based module design, including interpolator/decimator, filter, etc.
  • Top level self checking simulation, UVM imported

FPGA Design Manager

Jariet Technologies, Inc.
Redondo Beach, CA
05.2017 - 06.2021
  • Cortex A9/A53 CPU-based system design with AXI peripherals.
  • High-speed data transfer interface design with the JESD204 protocol.
  • Data processing using DDR4/HBM memory interface.
  • Host PC interface design through 100 GbE.
  • Self-checking testbench, UVM simulation.
  • Firmware design based on FreeRTOS.

Principal Researcher

NEWRACOM, INC.
Irvine, CA
07.2015 - 05.2017
  • 802.11ah/n/ax Wireless LAN PHY module design project.
  • Top integration and system verification for FPGA, ASIC design.
  • Cortex A9, M3 CPU, and AMBA BUS-based system design and verification.
  • C-to-RTL co-simulation environment, RTL-to-Netlist simulation checking automation.
  • CDC/Lint check, scenario simulation using DPI, UVM environment, formal verification, code coverage.

Principal Researcher

Samsung Electronics
Suwon, Korea
10.2013 - 06.2015
  • Digital & Media Communication Center, Camera Platform Lab.
  • Samsung NX1 DRIMe5 Design/Verification Engineer using SystemVerilog, Verilog, and Python.
  • Self-checking testbench, top-chip functional simulation, and connectivity check, code complexity check.
  • Bug prediction and estimation tool, issue tracking, and source code management system for the verification process.
  • Design block: UFA (USB for Accelerator, USB communication).

Senior Engineer

Samsung Electronics
Suwon, Korea
03.2009 - 09.2013
  • 1066 MHz Wafer BOT mDDR2 Test Method Design.
  • GHz signal test solution on wafer probing.
  • IR sensor-based multi-touch solution design using the Spray Search algorithm, pre/post filter, (Simulink floating, fixed modeling).
  • GHz Random Signal Generation and Test Technology Design.
  • Mobile Memory Real-Aware Memory Tester Design.
  • 1.6 GHz DDR3 Real-Aware Memory Tester Design (2009, Memory).

Dispatch Researcher

ETRI (Electronics and Telecommunications Research Institute)
Daejeon, Korea
03.2007 - 02.2009
  • DVB-S2 (Satellite-II) communication modem design.
  • Coware SPW modeling, C language evaluation (floating, fixed point).
  • Design block: Symbol Timing Recovery, Frame Sync Detector, Freq.
  • DVB-S2 FEC (LDPC) design.

Assistant Engineer

Samsung Electronics
Hwasung, Korea
03.2005 - 02.2007
  • Memory process engineer with world-first technology.
  • Advanced process design with automated thickness management.

Education

Master of Science - Communication and Multimedia SoC design

Ajou University
Suwon, Korea
01.2009

Bachelor of Science - Electronic Engineering

Ajou University
Suwon, Korea
01.2005

Skills

  • CPU-based system design
  • RTL coding using Verilog, SystemVerilog, and VHDL
  • Self-checking testbench design
  • Quick System prototyping using System-level modeling
  • Firmware development
  • Training and mentoring
  • FPGA design expertise
  • Test automation methodology with Python script

Publications

  • Efficient frame synchronization detector using modulation mode estimation for DVB-S2, Jin K. Choi, Yeoung J. Jung, Myung H. Sunwoo, Pan S. Kim, Dae I. Chang, Proc. IEEE International SoC Conference, 2007, pp.35-35
  • Efficient frame synchronization detector with automatic gain controller for DVB-S2, Jin K. Choi, Yeong J. Jung, Myung H. Sunwoo, Proc. 2nd International Symposium of Foundation of Emerging Information Technology, 2008, pp.179-188
  • Efficient synchronizer architecture using common autocorrelator for DVB-S2, Jae H. Lee, Jin K. Choi, Pan S. Kim, Dae I. Chang, Myung H. Sunwoo, Proc. IEEE International Symposium on Circuits and Systems, 2009, pp.1533-1536
  • PATTERN SYNTHESIS APPARATUS AND SEMICONDUCTOR TEST SYSTEM HAVING THE SAME, U.S Patent Application No.13/484481, 05/12

Qualifications

VerilogHDL, VHDL, SystemVerilog, C/C++, Python, Xilinx, Altera, USB/Ethernet, Memory Controller, PCI express, DMA, Microblaze/Zynq, NIOS, AXI/AVALON, Coware(Synopsys), SPW/SPD, Matlab Simulink, Visual Studio, ModelSIM, NC, VCS, ISIM, UVM, SpyGlass, Asccent, Defacto, OrCAD, PCB editor, PSPICE, Synplify Pro, XST, DesignCompiler, HLS/Forte(SystemC), PlanAhead, TimeQuest, PrimeTime, Formality, SoC-Encounter, Chipscope, SignalTap, Identify, Verdi, Virtual IO

Accomplishments

  • Marquis Who's Who
  • Issued by Marquis Who's Who Ventures LLC · Sep 2024

Timeline

Sr. FPGA Design Engineer

Amazon
06.2021 - Current

FPGA Design Manager

Jariet Technologies, Inc.
05.2017 - 06.2021

Principal Researcher

NEWRACOM, INC.
07.2015 - 05.2017

Principal Researcher

Samsung Electronics
10.2013 - 06.2015

Senior Engineer

Samsung Electronics
03.2009 - 09.2013

Dispatch Researcher

ETRI (Electronics and Telecommunications Research Institute)
03.2007 - 02.2009

Assistant Engineer

Samsung Electronics
03.2005 - 02.2007

Master of Science - Communication and Multimedia SoC design

Ajou University

Bachelor of Science - Electronic Engineering

Ajou University

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Jinkyu Choi