Summary
Overview
Work History
Education
Skills
Embeddedsystemprojects
Digitaldesignprojects
Languages
Timeline
Generic
Julie Kim

Julie Kim

Los Angeles,CA

Summary

Experienced ASIC/FPGA engineer with strong focus on digital design, SystemVerilog coding, and hardware simulation. Proven track record in delivering high-performance digital design solutions, collaborating effectively with cross-functional teams, and adapting to evolving project requirements. Known for producing reliable results and driving efficiency in complex engineering projects.

Overview

11
11
years of professional experience

Work History

ASIC / FPGA DESIGN ENGINEER

Boeing
El Segundo, California
10.2021 - Current
  • Develop RTL design to interface with hard macro IPs
  • Implement Vivado design methodology for synthesis, P&R, and static timing
  • Optimize timing by limiting fanout and combo logic, and adding pipeline registers
  • Write or integrate reusable test bench to verify design using Vivado / Cadence simulation tools
  • Write scripting languages (c-shell) to compile and simulate design

DENTAL ASSISTANCE / RECEPTIONIST

Family Dental
Long Beach, California
11.2013 - 05.2024
  • Chair side assistant, Dental x-ray technician, and Insurance billing

COMPUTER HARDWARE SALE ASSISTANCE

Zippy USA Inc
Irvine, California
09.2019 - 02.2020
  • Core consultant of Power Supply Models and Schematic Drawings

Education

Master of Science - Computer Engineer

California State University Long Beach
Long Beach, CA
01.2023

Bachelor of Science - Computer Engineer

California State University Long Beach
Long Beach, CA
08.2019

Skills

  • Simulation
  • Communication Protocol (AXI Stream, AXI Lite, APB)
  • FPGA programming
  • IP core integration
  • Place and route techniques
  • Timing analysis / Timing Closure (setup and hold violation)
  • ASIC design experience
  • Testbench creation
  • Lab testing

Embeddedsystemprojects

  • AUTONOMOUS ROBOT, A two-wheel dc motor was built to travel in a 3x8 cells (each cell is 17cmx17cm). The system was built to learn the environment and decide on the shortest path to follow, and was implemented on a microcontroller programmed in C to control the movement in real time via PID control system and DFS algorithm.
  • BLUETOOTH ROBOT, A serial communication was implemented with phone application to control 4 direction of the two-wheel dc motor.

Digitaldesignprojects

  • FPGA EMBEDDED SYSTEM, Voltage control design was developed by integrating existing ADC and VGA IP, and demonstrate the functionality by loading the netlist into Zybo board.
  • PIPELINED CPU DESIGN, The MIPS processor was built as five stages pipeline including hazard detection and forwarding unit with performance of 4x speed up.
  • NON-PIPELINED CPU DESIGN, The same processor was built as 32-bit integer architecture including a Barrel Arithmetic Shifter unit for arithmetic calculation.

Languages

Cambodian
Native or Bilingual
Chinese (Mandarin)
Elementary

Timeline

ASIC / FPGA DESIGN ENGINEER

Boeing
10.2021 - Current

COMPUTER HARDWARE SALE ASSISTANCE

Zippy USA Inc
09.2019 - 02.2020

DENTAL ASSISTANCE / RECEPTIONIST

Family Dental
11.2013 - 05.2024

Master of Science - Computer Engineer

California State University Long Beach

Bachelor of Science - Computer Engineer

California State University Long Beach
Julie Kim