Kanmani GobiKaliappanSubraamanian

• Enhanced verification quality with improved HVP to improve functional coverage.
• Identified critical bugs through regression testing, ensuring product reliability.
• Mentored junior engineers, fostering a collaborative work environment and improving skill sets.
• Verification for various DP products with different combination of video streaming w/protocol conversion as DP over USB4 , HDMI over DP2.0 and so on design at block level and top level.

Verification consultant at Meta ASIC division.

Verification for warper.

Develop/Updated existing test plan and test sequences.

Updated the existing environment to support changes in the new ASIC design.

• As a staff verification engineer, worked on various interface parts involving DP, HDMI, DSC, MIPI over past 10 years with Synaptics
• Playing lead role in verification for VESA Display Stream Compression IP across various products by Synaptics
• Developed verification environment using different methodologies like VMM and UVM
• Developed wrappers to enable communication between VMM in-house DP VIP with UVM based environment to enable re-use of in-house DP VIP
• Developed DPI task to enable C based DSC model to interface with VMM/UVM based verification environment for DSC verification across various products that involved DSC logic
• Involved in various stages of RTL verification ranging from block level to system level testing
• Lead verification activities for remote teams and sign-on successfully.

• As a verification engineer, worked on various activities in testing the video interface products
• Developed CTS test cases for DP src and sink behaviors
• Developed re-usable VMM based verification suite for DP RX, aimed at re-usability of the verification environment for any future DP products
• Developed test plan, test bench, driver, monitor and scoreboard to verify DP RX
• Developed function cover points, maintain nightly regression, debugging and sign on verification with high function coverage.

• As an ASIC verification engineer, worked on verification for AXI Sub-System , AXI2AXI Bridge, DMA controller, etc
• Developed verification suite using eRM methodolgy
• Developed the test bench components and test case using Specman/E language.

• As a consulting VLSI design engineer, worked for NetApp for verification for their VIRGO FPGA design
• Developed verification components and test cases in Verilog HDL to test all the flash operations, interfacing with PCIe, I2C bus
• Developed Makefile to compile and simulate the design and test environment
• Sign-on verification with 100% functional coverage.

• As a member of technical staff, played variety of role in various projects for various clients like Hamilton Standard, Roswell Collins, IBM, Xambala Inc
• As an independent reviewer, understand the specification of design under test, review the test plan and test cases to confirm accuracy of the design requirement with respect to test plan development and sign-on the activity
• As a verification engineer, dealt with different HDL and Object oriented languages and methodologies to develop the verification environment and component to verify the design.

• As a design engineer, worked on verification for 3-Port PWT router for Paradigm Solutions
• Developed verification components like transactors and scoreboards for router design using Open VERA RVM methodology
• Developed test case, simulated various scenarios, debugged on failing cases, reported design bug, sign on verification with 100% functional coverage.

• Train Engineering students on VLSI technology, which involves teaching the VLSI front-end design flow for ASIC development using EDA tools and HDL languages ( VHDL and Verilog HDL).

• As a VLSI Faculty, train engineering student on VLSI front-end design flow for ASIC's
• The job involves teaching HDL languages (VHDL and Verilog HDL) to design and develop RTL and test bench
• Hands on training on EDA tools to simulate the design under test.

• As a design engineer, designed and developed UART transmitter logic using VHDL and AMBA aribter logic using Verilog HDL.