Kannan Kuttykrishnan
Austin,TX
Summary
Dynamic engineering leader with over 23 years of experience in the semiconductor industry, specializing in System-on-Chip (SoC) development. Currently serving as Senior Director of Hardware Engineering for High-Performance Compute at Renesas Electronics Corporation, overseeing the RTL-to-GDS delivery of advanced ADAS, IVI, and Gateway Fusion SoC chiplets on the N3A process node, as well as MCUs for automotive applications. Proven track record in driving a global team of over 450 professionals across the USA, Japan, Vietnam, and India, fostering collaboration and innovation to achieve strategic objectives. Previous leadership roles at NXP, Marvell Semiconductor, and Intel Corporation have refined expertise in managing complex projects and delivering cutting-edge technology solutions that meet market demands.
Overview
25
25
years of professional experience
Work History
Sr Director, Engineering
Renesas Electronics USA.
02.2024 - Current
- Leading a Global Engineering Organization spread across USA, Japan, Vietnam and India with over 450+ engineers across SOC/MCU Designs.
- Focusing on Physical Design in the development of RCAR Gen5 roadmap for ADAS; IVI; Gateway Fusion SOC & Chiplets with AI Accelerators for Automotive SDVs on N3A tech-node. Taped out the industry first 3nm Automotive SoC.
- Driving RCAR MCU execution for automotive applications with a rich product portfolio of over 10 MCUs Tape-outs per year
- Initiated Structural & Cultural transformations through the deployment of Horizontal Platforms and Domain Workgroups to enable predictable & efficient execution & development with focus on quality
- Drove key engineering initiatives for AUC reduction, Cycle time reduction, Vendor consolidation, Quality Metrics and Dashboards and Skill Augmentation & Development.
- Established a brand-new India engineering site at Noida, for high-end SOC development, with record timeline from team inception to first Tapeout (5 Quarters)
Sr Director/Director , SOC Implementation
NXP Semiconductors, N.V.
09.2017 - 02.2024
- Responsible for SOC Physical Implementation horizontal & delivery from Synthesis -> GDS, and Power Integrity Signal Integrity domains
- Managed engineering sites (~80 member team) across USA, Europe & India
- Taped-out of 3+ SOCs per annum spanning high end Automotive (domain controller, vehicle, computer, Radar SOCs), Edge Processors (ultra-low power MCUs & MPUs) & Digital Networking SOCs
- Responsible for several initiatives on AUC/Device cost reduction and First Time Right initiatives
- Deployed several key initiatives for efficiency and skill developments within a short span
Sr Mgr Engineering
Intel Corporation, Inc
09.2015 - 09.2017
- Leading SIP Physical Design for ATOM
- Build Grounds up and Lead the Physical Design team responsible for RTL2GDS delivery for mid range performance ATOM processors for internal intel customers.
Sr. Staff Manager
Marvell Semiconductor
06.2006 - 08.2015
- Led the Physical Design team of 35 members. responsible to Deliver the Application SoC (PXA family) Processors and RF transceiver processors.
- Team responsibilities includes Synthesis, PNR, STA & PV Signoff.
- In addition to the SoC delivery, team was responsible for delivery of Subsystems(DDR,PCIE,ARM Cores) across organizations.
- Transformed Austin site from Subsystem delivery site to a complete SoC delivery.
NCG to Manager
Intel Corporation
02.2001 - 06.2006
- Managed Globals team that was repsonsible for PG Design and Validation, Signal Integrity, Supply Noise Integrity Simulations and Custom Power management circuits.
- Analog Design of Oscillators (13MHz & 32KHz), Linear Regulator and DC2DC Converters for the Xscale Processor family
- Design and Validation of special power manager circuits like high-speed level shifters, custom circuits, power switches, bias generators.
- Performed Analog Mixed Signal (AMS) simulations for low power mode entry/exit and other startup and reset sequences.
- Power Grid Spec and Design and Spice model builds
- Data-path design for custom co-processors.
Education
Master of Science - Electrical Engineering (VLSI)
Wright State University
Dayton, OH12-2000
B.E - Electronics And Communication Engineering
SRM Engg College
India06-1999
Skills
- Cross-regional management experience
- Strong technical management with results orientation & delivery focus
- Delivered Key SOC programs to success at ; Intel, Marvell, NXP & Renesas
- Skilled in managing concurrent projects and timely product delivery
- Team building and retention expertise
- Diversity and inclusion advocate
Timeline
Sr Director, Engineering
Renesas Electronics USA.
02.2024 - Current
Sr Director/Director , SOC Implementation
NXP Semiconductors, N.V.
09.2017 - 02.2024
Sr Mgr Engineering
Intel Corporation, Inc
09.2015 - 09.2017
Sr. Staff Manager
Marvell Semiconductor
06.2006 - 08.2015
NCG to Manager
Intel Corporation
02.2001 - 06.2006
Master of Science - Electrical Engineering (VLSI)
Wright State University
B.E - Electronics And Communication Engineering
SRM Engg College