15+ Years of experience in SOC/ASIC/FPGA Verification/Debugging and simulation.
Experience in ASIC Verification Plan Development, coverage-driven constraint random Test Bench development using HVL languages like Vera, and System Verilog with OVM/UVM/C.
Developed environment components such as Bus functional models, Protocol Monitors, Checkers, and Generators using System Verilog/Vera.
Experience in developing Open Verification Components and Universal Verification Components like env, agent, sequences, sequencers, drivers, monitors & scoreboard. Developed OVM/UVM components from scratch & migrated OVM to UVM .
Have experience in working with 3rd Party VIP’s like AXI/AHB/APB/PCIE Developed directed and random test cases in Verilog, System Verilog, OVM, UVM Have verified multiple blocks at Unit/IP level, Subsystem level & chip top level .
Did verification of Cortex ARM/Synopsys ARC/Cadence Tensilica Core-based environment with C/System Verilog/UVM/OVM benches Experience in RTL/GLS/SDF simulations.
Protocol experience in Intel IOSF Sideband/Primary, AMBA AHB, AXI, APB, USB 2.0, PCIE, IEEE 802.11b WLAN MAC technology, and project-specific protocols. Knowledge of Shell, Perl and Make file scripting.
Overview
20
20
years of professional experience
Work History
Pre-Silicon Verification Engineer
Intel Corporation
05.2020 - Current
As a Verification Engineer at Intel, I played a critical role in validating several advanced components across various projects, including Panther Lake, Lunar Lake, Kenai Ridge, and Niagara Summit
Led full validation of Wi-Fi, Top, and CNVB modules
Created and updated verification plans and testbenches in System Verilog/OVM
Developed directed and random test cases, managed regressions, debugged issues, and tracked coverage
Developed verification plans and updated testbenches
Designed and executed test sequences in System Verilog/OVM
Managed constraint random regressions, identified and debugged issues, and enhanced coverage
Oversaw validation of Bluetooth and Top modules
Created detailed verification plans and test cases
Conducted regression tests, debugged failures, and reviewed coverage with cross-functional teams
Developed verification environment with System Verilog/UVM and C reference model
Integrated VIPs, created UVM components, and designed comprehensive test cases
Ran RTL simulations, debugged issues, and verified chip top-level functionality
Created UVM components and test cases for header extraction
Conducted RTL simulations, debugged issues, and achieved 100% coverage through detailed testing
Performed firmware-based RTL debugging and created GLS/SDF environments
Executed zero delay/SDF simulations, identified timing issues, and collaborated with designers for fixes
Senior Verification Engineer
Cerium Systems Inc.
09.2015 - 04.2020
I worked as a contract employee for Intel and Broadcom during this period
Developed the verification environment using System Verilog/UVM
Integrated MPS developed from python for accurate test vector creation and reference model processing
Created UVM components for interface testing and block verification
Conducted concurrency testing and set up Gate Level Simulations (GLS)
Developed SDF simulation environment and test plans for block verification
Designed sequences and tests for concurrent block simulation
Created a dual PMVC setup and developed components for sideband messaging and reactive events
Validated Dynamic Voltage and Frequency Scaling sequences
Modified Command Streamer BFMs, developed functional coverage points, and ran regression tests
Analyzed specifications, prepared test plans, and developed sequences and test cases
Senior Member of Technical Staff
Xingtera Inc
06.2012 - 09.2015
I played an active role in the Design Verification of the XT1200/XT1100 G.hn chips developed by them
Migrated the verification environment from OVM to UVM for the XT100 G.hn chip and executed regression tests to ensure stability
Developed random test cases for the TSAR module, enhancing test coverage and verification depth
Improved test coverage by identifying gaps and creating additional test cases for the XT100 G.hn chip
Created and executed a detailed test plan for LLC Ingress/Egress Engine and GMAC’s TSAR Module, ensuring thorough block-level verification
Developed key components including LLC frame class, constraint random generator, monitor, G.hn receive BFM, and Mbuf converter in System Verilog
Conducted coverage analysis using IMC tools and achieved effective coverage for LLC Ingress/Egress Engine
Performed throughput calculations at the GPHY interface for the GMAC’s TSAR module
Managed end-to-end full-chip verification for XT1200 G.hn chip, including connectivity verification between chips and blocks
Set up a loopback environment for SAR verification using Open Verification Components
Verified full-chip functionality with ARM simulation using C/System Verilog, ensuring robust integration of all blocks and interfaces
Senior Engineer
L&T Infotech
10.2010 - 05.2012
I worked for the client Freescale during this time
Developed comprehensive test plans for QuadSPI/RLE and CLASS/SAP blocks, ensuring thorough system-level verification
Ported and created stimuli, including adapting VIP from other projects and developing new ones for QuadSPI/RLE and CLASS systems
Modified driver wrappers to fit specific project environments, enhancing compatibility and functionality
Reported and resolved bugs related to connectivity, parameters, and other issues, improving overall block performance
Conducted coverage analysis, achieving high toggle coverage (97% and 100%) by identifying and addressing coverage gaps
Adapted and resolved connectivity issues for the CLASS interconnect system and SAP debug features
Ensured complete memory and register coverage for the SAP block, achieving 100% toggle coverage
Senior Verification Engineer
WhizChip Design Technology Pvt Ltd
06.2005 - 05.2010
I worked for clients like Netlogic, RMI and NVIDIA during this tenure
Developed and executed detailed test plans for various blocks including USB2.0 subsystem, CAM Controller, and AMBA AXI BFM
Built and adapted testbenches for blocks such as USB2.0 subsystem and OTG Host, integrating new blocks as required
Created and ran directed and random test cases for comprehensive verification of 32-bit and 64-bit EHCI, OHCI controllers, CAM Controller, and USB functionalities
Conducted performance testing to ensure system efficiency for USB subsystems and other components
Replaced BFMs (Bus Functional Models) with updated versions, including the conversion of OCPBFM to SBUS BFM
Integrated memory PLI for comparison and managed bug filing and resolution
Verified Master BFM functionality by creating a slave design and developing detailed test plans and cases
Managed and executed PCIe verification tests at the full-chip level, conducting over 100 gate-level tests and resolving issues in collaboration with the implementation team
Improved test coverage and functionality verification for USB controllers in the Monet Portable Media Player Chip project
Achieved thorough block verification for the CAM Controller, validating protocol handshakes and FIFO operations
Ensured system performance met specifications for USB2.0 subsystem and successfully verified the functionality of various USB controllers and protocols
Member Technical Staff
Hellosoft Pvt Ltd
06.2004 - 05.2005
I worked in WLAN MAC project
Gained an understanding of the 802.11b MAC protocol and design
Developed RTL for the MAC, including DCF and TX parts
Verified the MAC RTL by writing and executing test cases
Education
Bachelor of Science - Electrical And Electronic Engineering
System Software Engineer - Embedded Systems at Intel Corporation - Intel FlexSystem Software Engineer - Embedded Systems at Intel Corporation - Intel Flex