KARTHIK WALI
Summary
Dynamic ASIC Design Engineer with extensive experience in CPU and peripheral IP design, specializing in RISC-V and ARM architectures. Expertise in RTL design, synthesis, and power analysis, with a focus on integrating complex functional blocks to enhance system performance and efficiency.
Overview
12
12
years of professional experience
Work History
ASIC Design Engineer
Amazon Lab126
Sunnyvale
06.2021 - Current
- Designed and integrated RISC-V IP with co-processor interface for enhanced compatibility.
- Implemented microarchitecture for IOMMU unit, boosting system performance.
- Developed data path for floating point instructions to improve processing efficiency.
- Executed DW Conv2D instruction data path implementation, optimizing operational speed.
- Integrated microarchitecture of PCIe, IOMMU, GIC, and MSI64 encapsulator for synergy.
- Created MSI interrupt interface with coalition and CSR registers to streamline functionality.
- Conducted synthesis and timing optimization to elevate design performance.
- Developed RTL DV, lint, and CDC agents for robust architecture validation.
ASIC Staff Design Engineer
Synopsys
Mountain View
09.2020 - 05.2021
- Worked on HLA to add new security and safety features to ARC EM for next version of EM cores.
- Modified RTL based on the proposed new features.
- Worked on customer requirements to modify EM core for feature set requested.
Senior Design Engineer
LG Electronics Mobile Research USA LLC
San Jose
12.2014 - 09.2020
- Designed a 4-stage high speed RISC-V core for RV32IM specification.
- Worked on integrating Single precession Floating-point instruction support to RISC-V core.
- Implemented Softmax function with IEEE754 Single precession Floating Point and Fixed Point as an accelerator block.
- Designed a packet transfer and synchronization module across scalable cores.
- Designed an arbiter for instruction fetch across scalable cores.
- Worked on high speed design of the data path of coprocessor/DSP unit.
- Conducted LEC, Spyglass lint checks, synthesis, and power analysis of IP.
- Automated synthesis using Genus, and power analysis using Power Artist for scalable cores and different design and technology options.
- Managed design changes for the register block, data pipeline control, and replay queue blocks.
- Designed automatic mode changes for SLC IP.
- Implemented dynamic architectural clock gating, way-based shutdown and light sleep mode for a SLC IP as a power saving technique.
- Worked on design of ELA Trace Interface for SLC IP.
- Integrated the SoC with dual ARC cores and peripherals for the IoT platform.
- Micro-architected and Designed an interface for Batching sensor data from Multiple I2C Slave and SPI Slave.
- Made IP configurable for memory sizes, data width and pipeline stage options.
- Designed System Registers and Memory Wrappers.
- Modified the RTL for FPGA and Generated FPGA Bit files for testing the SoC platform on Kintex FPGA Boards.
- Developed directed connectivity test cases in C to verify peripheral functionality.
- Established the verification flow for real-time software test cases for the SoC.
- Developed power analysis flow using Power Artist to accurately assess power consumption for the SoC.
- Directed team of verification engineers to establish verification flow and test cases, ensuring thorough validation of the SoC.
- Directed team of verification engineers to establish verification flow and test cases, ensuring thorough validation of the SoC.
Education
MS - Electrical Engineering
Illinois Institute of Technology
Chicago01-2014
Skills
- Cadence tools and Verilog
- NCSim and ModelSim
- QuestaSim and Xilinx Vivado
- Synopsys Design Compiler
- Genus and RTL Compiler
- UVM and SystemVerilog
- SpyGlass and Verdi tools
- Linux operating system
- Git version control
- MATLAB programming
- Power Artist
Timeline
ASIC Design Engineer
Amazon Lab126
06.2021 - Current
ASIC Staff Design Engineer
Synopsys
09.2020 - 05.2021
Senior Design Engineer
LG Electronics Mobile Research USA LLC
12.2014 - 09.2020
MS - Electrical Engineering
Illinois Institute of Technology