KARTICK SRIDHAR
Bengaluru,Karnataka
Summary
I am a Design-for-Test (DFT) Engineer specializing in developing and implementing DFT architectures for complex SoC and VLSI designs. With hands-on experience in scan insertion, ATPG, MBIST, boundary scan (IEEE 1149.1/1149.6), and silicon bring-up, I excel at ensuring testability, manufacturability, and high fault coverage. My background spans across DFT implementation, verification, ATE debug, and post-silicon validation with focus on yield optimization, timing closure, and test automation using Python, TCL, and Perl scripting.
Results-driven engineering professional with focus on product development and innovation. Known for driving impactful projects and delivering high-quality solutions. Strong emphasis on team collaboration and adaptability to changing requirements. Proficient in problem-solving and product lifecycle management.
Overview
10
10
years of professional experience
1
1
Certification
Work History
Product Engineer
Mettlesemi Systems and Technologies
08.2025 - 10.2025
- I worked for a client involved in in DFT testing, ATE Silicon bring up and Post-Silicon validation with emphasis on yield analysis to detect and predict potential defects.
Product Development Engineer
Intel Corporation
02.2022 - 11.2024
- I have hands-on experience in both pre-silicon verification using DFT tools and post-silicon validation for CPUs, GPUs, and SoCs across next-generation devices. My responsibilities included requirement analysis, test case development, automation, and functional debugging of new chip features to optimize yield and reduce test time. I applied Python to convert mathematical algorithms into executable programs, enabling automated defect detection, data analysis, and validation workflows. I collaborated with global teams across Malaysia, Ireland, Israel, and the USA to align deliverables and project execution strategies.
- Below are details of the key skills and technologies I learnt during my tenure.
- End-to-end silicon testing from pre-silicon readiness to post silicon bring up and production.
- Understanding DFT architecture for subsystems and SoCs for logic and memory tests.
- Collaborate with IP teams, Systems, and Architecture teams to derive requirements and align DFT goals for IPs, subsystems, and SoCs.
- Work closely with Product and Test Engineering teams to understand test needs, provide DFT solutions, debug issues, and optimize test costs.
- Proficient in TCL and Perl Scripting, facilitating automation in DFT processes and performing functional verification using UVM.
- Power management features, mode optimization, voltage margining and checking
- Created Scripts for debugging compression using Siemens Tessent Testkompress and MBIST patterns on ATE.
- Python programming for incorporating the FSM logic to enable the overall process of early boot config functional flow.
- Resolving DRC and scan chain trace issues to enhance test efficiency.
- Used JTAG methodology IEEE1149.1 at the chip level and IEEE 1500 at the core level for testing various IPs such as PCIE, USB, GBE in different dies.
- Wafer testing and packaging to test multiple dies and units through a thermal socket head and a tester interface unit.
- Analyzing and inspecting test patterns in various stages of reset to improve yield and reduce test time in wafer sort and class test programs.
- Producing automated test patterns (ATPG) using Siemens Tessent for inspecting manufacturing defects
- Used Synopsys Fusion Compiler for performing scan chain insertion.
- Data analysis tools like Crystal Ball, Microsoft Excel and JMP for analyzing yield data.
- Flash EDA solution for performing full chip validation using UTAG and STIL (Standard Test Interface Language)
Software Engineer Trainee
Harvest Software Solutions, LLC
03.2021 - 02.2022
- I was responsible for translating project specifications and problem statements into detailed logical workflows to design and develop front-end interfaces integrated with backend data structures for proprietary software solutions. My work incorporated Machine Learning techniques and adhered to software development life cycle (SDLC) best practices. I also engaged directly with clients to gather and validate business requirements, and incorporated User Acceptance Testing feedback to refine production-ready implementations.
Data Scientist Intern
Byte Consulting Inc.
07.2020 - 03.2021
- Served as a Data Scientist at Spryte Labs, where I managed cloud-based data pipelines and implemented machine learning models to optimize client–vendor matchmaking on the Spryte App. The platform supported vendor staff management for large-scale organizations, enhancing operational efficiency and service alignment.
One-year Industrial Experience as part of academics
HCL Technologies (Innovation Labs)
01.2016 - 06.2017
- During this year, I was introduced to corporate workflows and gained hands-on experience across the complete software development life cycle and product development processes. My functional exposure to diverse domains—including banking, commodities markets, and health sciences—sharpened my ability to adapt technologies to varied requirements. This experience enhanced my understanding of how business needs influence product design and performance.
- Developed a machine learning model to filter spam words from official email content using Naive Bayes and Gary Robinson’s technique, implemented in JavaScript
- Executed an IoT-based motion detection and commodities trading project using inertial sensors on Raspberry Pi for data acquisition; designed and deployed a frontend web dashboard with rich analytics
- Collaborated with Deutsche Bank’s Transaction Banking Applications team, engaging with product specialists and subject matter experts to support ongoing system enhancements.
Summer Internship
HCL Technologies (Innovation Labs)
06.2015 - 09.2015
- Led the setup of a scrum board to manage and organize task workflows during the visitor system management software project. Applied agile principles to ensure seamless development and collaboration across sprints.
- Structured weekly deliverables into sprints aligned with agile methodology for efficient progress tracking.
- Designed a user-friendly front-end interface for visitor management using HTML, CSS, and JavaScript
- Implemented timely UI updates based on feedback from the administration team to enhance usability.
- Applied UX design best practices to tailor the interface for diverse user roles and personas.
Education
Master’s Degree - Electrical & Computer Engineering
University of California, Irvine
Irvine, California, USA01.2020
BEng (Hons) - Electrical & Electronics Engineering
The University of Manchester
Manchester, United Kingdom01.2018
Skills
- IC Design Tools: Cadence Virtuoso, Keysight Advanced Design System (ADS)
- PCB Design tools: OrCAD, Altium, NI Multisim
- EDA tools: Siemens Tessent, Cadence Innovus
- Hardware description languages: VHDL, System Verilog, UVM Methodology
- Programming languages: C, C, Java, JavaScript, PHP, Python, MATLAB, TCL, Perl
- Embedded device programming: PIC microcontrollers, Raspberry-pi, and Arduino
- Machine learning tools: Sklearn, TensorFlow, Pytorch, OpenAI, Mujoco
- Cloud Technologies: Firebase database, Cloud Firestore, Google Data Studio
- Version Control tools: Git, Github, Bitbucket
- Databases: MySQL, Big Query
- Operating Systems: Linux, Unix, Windows, ChromeOS, Android Studio
- Microsoft tools: MS Word, MS Excel, MS Powerpoint, MS Visual Studio
Certification
- Machine Learning Specialization by Andrew Ng https://coursera.org/share/ce8227f4f9b824a9d9f15bdbe9384806
- FPGA Design Learning VHDL: https://www.udemy.com/certificate/UC-HJ6EFTPQ/?utm_campaign=email&utm_source=sendgrid.com&utm_medium=email
- Cluster Analysis and Unsupervised Learning in Python: https://www.udemy.com/certificate/UC-ABGQ2YMA/?utm_campaign=email&utm_source=sendgrid.com&utm_medium=email
- VLSI CAD Part II: Layout: https://coursera.org/share/bb5723a048ad62d88550969c7756187
- Design for Testability from Maven Silicon, Bengaluru
Timeline
Product Engineer
Mettlesemi Systems and Technologies
08.2025 - 10.2025
Product Development Engineer
Intel Corporation
02.2022 - 11.2024
Software Engineer Trainee
Harvest Software Solutions, LLC
03.2021 - 02.2022
Data Scientist Intern
Byte Consulting Inc.
07.2020 - 03.2021
One-year Industrial Experience as part of academics
HCL Technologies (Innovation Labs)
01.2016 - 06.2017
Summer Internship
HCL Technologies (Innovation Labs)
06.2015 - 09.2015
BEng (Hons) - Electrical & Electronics Engineering
The University of Manchester
Master’s Degree - Electrical & Computer Engineering
University of California, Irvine