Overview
Work History
Education
Skills
Certification
Timeline
Generic

Karunakara Gudredigari

San Jose,CA

Overview

12
12
years of professional experience
1
1
Certification

Work History

Staff Engineer

Qualcomm
04.2019 - Current
  • Responsible for PNR and STA , DDR subsystem for latest cutting edge technologies like 2,3,4 and 7 nm
  • Handled Multi-power domain subsystem and designed to meet all the sign-off requirements, Low power design implementation .
  • Custom clock tree building for high frequency subsystems with high-speed buffers and eco planning which helps the timing and DCD closure
  • Responsible for Partitioning and floor planning the subsystem and provide the feedback to cross teams and
  • Timing closure for multiple subsystems such as high-speed designs and low power blocks
  • Actively worked and provided quick support Timing and CLP/IR drop closure.
  • FV/CLP signoff for various projects and setting up the flow for Early GDS release
  • Setup the flow for quick implementation of channels, pre-placement and pre-routing with help of TCL and sign off with Timing and Redhawk
  • Various Flow enhancements achieve quick release .
  • Quickly adapted the design changes and planned for early closure.
  • Established to case study for to achieve the better IR drop , includes RDL,BUMP and Special PG planning .
  • Skilled at working independently and collaboratively in a team environment.

Senior design engineer

Altran US crop
08.2018 - 04.2019
  • Worked for Qualcomm as full, consultant
  • Responsible for Placement and route, Timing closure for channel subsystem
  • Responsible for timing closure for high-speed bus
  • Worked on sub system clock tree building and planning
  • Handled complete flow for couple blocks from floorplan to GDS.

Senior Member Technical engineer

Altran India Inc
06.2013 - 08.2018
  • Worked for various projects from Test chip to Product chips with 7 and 10 nm technologies, across different tools
  • Responsible for PnR and STA , PV closure for various IP's.
  • PPA experiments for couple of test chip blocks.
  • Worked on couple of High frequency IP (SERDES) for different foundries, BUMP , PG and High frequency timing closure .

Physical Design Engineer

AppsConnect technologies
03.2012 - 06.2013
  • STA intern and supported the quick STA flow, responsible for Timing closure.

Education

Master of Science - VLSI And Embedded Systems

JSSATE

Electronics And Communication

L.C.R College of Engineering And Technology
Chennai,inida

Skills

  • Professional SKILLS:
  • Floor-plan, Partition, Placement ,CTS and Routing , STA Prime Time , LEC , CLP
  • TOOLS: Cadence SoC encounter/Innovus , Synopsis ICC/ICC2 and FC
  • Synopsys Prime Time for STA
  • Conformal LEC & CLP
  • StartRC
  • Calibre for LVS and DRC

Certification

Advanced certificate training program in VLSI, MSRIT - 2009

Timeline

Staff Engineer

Qualcomm
04.2019 - Current

Senior design engineer

Altran US crop
08.2018 - 04.2019

Senior Member Technical engineer

Altran India Inc
06.2013 - 08.2018

Physical Design Engineer

AppsConnect technologies
03.2012 - 06.2013

Master of Science - VLSI And Embedded Systems

JSSATE

Electronics And Communication

L.C.R College of Engineering And Technology

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Karunakara Gudredigari