Kesavaram Challapalli

Block level verification read controller buffer.

•Implemented new tests in accordance with test plan specifications.

•Enhanced test bench to meet project requirements and improve testing accuracy.

•Developed and validated assertions and checkers, ensuring adherence to quality assurance standards.

•Conducted code coverage and functional coverage analysis, verifying test completeness and effectiveness.

•Debugged regression failures to identify root causes and solutions.

Verification SPI and AHA(ASK demod hardware accelerator) at SOC level.

•Developed comprehensive test plan, test cases, and regression suite.

•Integrated SPI Synopsys VIP into SoC level verification environment.

•Developed C tests for CPU functionality, focusing on interrupts and data transfer validation.

•Built checkers, assertions, and functional coverage models to improve validation rigor.

•Verification SPI and AHA(ASK demod hardware accelerator) at SOC level.

Utilized JIRA to identify and report numerous bugs effectively.

•Analyzed failing regressions while ensuring code and functional coverage accuracy.

•Performed gate-level simulations to identify and analyze corner case failures.

•Communicated findings directly to design team for resolution.

Top level verification of loop controller block in wireless charger (client Renesas).

• Developed vplan from scratch according to specification.

Implemented test cases according to vplan to verify all supported features.

• Coverage and assertion implementation to check for coverage.

• Coverage analysis and writing directed test cases.

• Debugging failures and root cause analysis.

SOC verification of Ethernet(Client SemiFive).

• Coded test cases to verify all the features supported.

• Debugged failures and root cause analysis and suggested fix.

• Performed different command operations such as READ, WRITE.

• Around 15 different MAC features were coded and tested.

• Worked on performance tests and jumbo features.

SOC verification of QUPSS (Qualcomm Universal Peripheral subsystem).

• Verification of QUPSS at SOC level for all supported serial engines and protocols.

• Test generation, address map checking for the current version, test config updation.

• Regression debug and coverage analysis.

• Analysing toggle coverage adding exclusions and writing tests to cover the uncovered toggles.

IO Visualization block verification at SOC level (Client ARM).

Verified smmu features of IO block.

• Connectivity checking using UVM tests.

• Coverage analysis and formal connectivity testing.

• Regression failures debugging and scoreboard enhancement.

Verification of Infineon’s SRI protocol bridges at IP Level.

Verified bus bridges at IP level, ensuring compliance with protocol specifications.

• Debugging the failing tests in regressions and fixing them.

Analyzed toggle coverage, added exclusions, and wrote tests to cover uncovered toggles, improving overall verification accuracy.

• Soak testing of bridges with fixed no of seeds, running regressions and fixing the failures.

Verification of Intel Specific Test Chip at full chip level

• Brought up testbench, coded new tests, and enhanced existing tests for current version.

• Debugged failures from regression results, ensuring timely issue resolution.

• Developed coverage metrics to evaluate effectiveness of tests.

• RAL model generation and integrating.

• Mentoring juniors

Verification of Intel Specific (IOSF2AXI) Bridge (IP Level).

Enhanced scoreboard for the new features added in the current version.

Validated Platform Controller Hub (PCH) hardware, ensuring optimal functionality and reliability.

• Identifying the test scenarios, Coding new tests at fc level for low power verification of individual IPs, all IPs and fabrics present in PCH.

• Clock gating/Power gating an IP and Clock waking/power un-gating.

• Checking on clock gating & power gating features of an IP at Full Chip level.

• Debugging the failures, back tracing, reporting issues and filing RTL bugs.

• Enhancing legacy tests according to the project and debugging.

• Supporting junior team members.

Verification of Camera Interface Block in a Display Subsystem.

• Extracting the data paths that need to be verified.

• Configuring all the necessary IPs in the subsystem.

• Creating directed test cases to verify the data flow in the given data path.

• Configuring CAMIF for required i/p and o/p formats.

• Bringing up the test bench.

• Verifying data paths between camera and other blocks in Display subsystem.

• Compared RTL output with the c-model output.

• Calculated camera interface performance by measuring AXI bus transaction reads and writes.

Verified ISP block functionality in display subsystem.

• Bringing up the environment.

• Configuring the sub IPs of ISP system.

• Creating the Directed test cases with given input format and output format types.

• Verifying all the data paths in ISP block.

• Developed data path test cases for ISP chain to verify data flow between 10 IPs.

• Calculated Performance of ISP chain block in terms of axi reads and writes happened in a given transaction.

• Verified the output data with c reference model.

Completed module-level verification of Interpolator, DMA Controller, and SIGCON CPU in SL1001 chip.

• Verified Interpolator with different types of sampling rates and with different input formats.

• Verified data traffic between RS CPU and VIT output by using DMA

• Changing the register configuration according to the required test case scenario.

• Developed assembly language test case for SIGCON CPU verification.

• Conducted code coverage analysis for Interpolator and DMA.

Verification of DMA controller .

• Conducted code coverage analysis for Interpolator and DMA to ensure comprehensive testing.

• Created a simple system Verilog test bench for verifying DMA controller.

• Verified DMA controller with single master and multiple masters.

• Verified functionality of DMA controller through rigorous testing.

• Generated random data inputs for DMA, enhancing test reliability and robustness.

• Implemented constraints for address and data fields to ensure data integrity during DMA operations.