Kowshik Chandrasekar
Austin,TX
Summary
Detail-oriented verification engineer with 9 Years of experience in AI/Hardware Design Verification field, exploring challenging opportunities.
Overview
12
12
years of professional experience
Work History
AI ASIC Design Verification Engineer
Meta
2022.07 - Current
- Contributed to myriads of tasks in AI Training and Inference Accelerator chip project during different phases of the project at Meta.
- Defined testplan and brought up a vertically and horizontally reusable UVM based verification environment for verifying the local memory block used for AI compute tasks in the AI Training and Inference Accelerator chip project. Also helped verify some of the custom instruction behavior of the command processor in the project. Flushed out multiple design bugs in the process with no issue escaping to higher/next level verification hierarchies.
- Came up with the python based Register abstraction layer parsing the CSRGEN output files for verifying DMA functionality of the Debug feature using python based Test Environment in the training and inference accelerator project. This infrastructure has been deployed on all the projects now helping us efficiently check out config space access verification.
- Quickly assessed requirements, defined test plan, and brough up a reusable Test Bench from scratch for the trace/telemetry feature which was proposed after the AI chip project took off and executing. Successfully flushed out all issues promptly ensuring the feature's integration into the processing element subsystem, received recognition for its functionality and the use case of the feature in analyzing the performance the AI chip wrt various industry standard AI workload. Subsequently, led verification efforts as the Point of Contact (POC) for the feature's extension into the messaging engine subsystem
- Recognizing the need for enhanced regression maintenance, developed a Regression Dashboard and bucketing utility using Python and SQL. This initiative streamlined organization, archival, and reporting of miscellaneous failures, significantly boosting team efficiency in regression maintenance and overall project management.
AI ASIC Design Verification Engineer
Microsoft
2021.05 - 2022.06
- Contributed to AI accelerator silicon project for Azure server by owning the verification of custom IP which was designed to handle various telemetry data from the chip. Came up with the Robust and modular Test Environment that can be easily updated for any feature updates and reused across projects.
- As the project matured, was given an opportunity to lead a team of contractors and new collage grads to deliver Structural Vector Format (JTAG based) files that has power-on preambles to Post silicon flushing out all the reset flow related and design issues early in the project life cycle and got awarded my promotion for the contribution in a relatively short time at the company.
- Helped verify miscellaneous IP connectivity and data paths at SOC level, writing and debugging C++ based connectivity tests. This task is crucial for the AI inference accelerator chip to be functioning as per expectation.
- Came up with the excel sheet based Regression bucketizing script for efficient maintenance of project regressions and helped the verification organization adopt this infrastructure.
SOC Design Verification Engineer
Intel
2016.05 - 2021.04
- Displayed great efficiency by handling validation of multiple DFT & DFD features which includes from defining test-cases to bringing up TE for executing test-cases
- Established great collaboration with designers & architects for constantly communicating the design bugs and concerns
- Drove initiatives like meta-flop modeling, Xprop enabling across validation teams to ensure and enhance the quality of design
- Put together training materials and organized a forum for communicating the ideas/concerns to new validators and designers
- Awarded with promotion for my contribution within a relatively short span of 15 months
- Got a chance to contribute to Power Management Verification - Handled verification of different architectural/Micro-architectural flavors of ActivePM flows, in both simulation and emulation platform
- Supported other integration verification teams by providing simulation PM templates (UVM based SW Design patterns) for integrating their IP traffic to validate the PM flows
- Put together effective emulation testcases for stressing the PM flow using Perspec system Verifier.
- Developed and enabled Post-processing checkers and coverage in Python that parses and uses logs created by DPI mechanism
- Quickly established myself as a go-to person for any PM related issues assisting Post-silicon teams by reproducing corner case issues seen on silicon in emulation and simulation platforms by tweaking tests and modeling different scenarios
- POC for HW/FW integration - developed smoke-alarm kind of script that detects the overriden failures in Continuous integration flow and block the changes from landing.
Post-Silicon Functional Test Writing Intern
Intel
2015.06 - 2016.03
- Automated Regression reporting and regression health indicators updates using perl
- Developed IA-32 Assembly tests to validate the core architecture
- Responsible for maintaining regression content and debugging failures.
Web Testing - Automation Engineer
Infosys Consulting Inc.
2012.11 - 2014.07
- Automated web-page testing using Selenium & Java applications
- Gained expertise on Java & HTML scripting.
Education
Master of Science in Electrical And Computer Engineering -
Portland State University
Portland, OR03.2016
Bachelor of Science in Electrical And Electronic Engineering -
Anna University
07.2012
Skills
- Critical Problem Solving
- Testing Methodology
- SVA
- UVM
- Python
- Clean code
- Efficient Debugger
- Constrained Random (CRV)
- Functional Coverage
Timeline
AI ASIC Design Verification Engineer
Meta
2022.07 - Current
AI ASIC Design Verification Engineer
Microsoft
2021.05 - 2022.06
SOC Design Verification Engineer
Intel
2016.05 - 2021.04
Post-Silicon Functional Test Writing Intern
Intel
2015.06 - 2016.03
Web Testing - Automation Engineer
Infosys Consulting Inc.
2012.11 - 2014.07
Master of Science in Electrical And Computer Engineering -
Portland State University
Bachelor of Science in Electrical And Electronic Engineering -
Anna University
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