Kranthi Kumar
Chandler,US
Summary
Senior Process Engineer with 8 years of semiconductor experience specializing in ALD metal deposition and NAND memory device testing. Proven contributor to high volume manufacturing environments, with a strong record of improving yield, reliability, and throughput through data-driven process optimization. Experienced in transferring ALD metal processes from R&D to production and supporting large-scale equipment upgrades. Deep expertise in SPC, DOE, root cause analysis, and process integration for memory technologies. Recognized for hands-on troubleshooting, rapid issue resolution, and effective collaboration with device, integration, and manufacturing teams.
Overview
9
9
years of professional experience
Work History
Senior Process Engineer I, Metal Logic Team
ASM America
Phoenix, US
07.2023 - Current
- Developed and optimized BEOL Mo deposition processes on ASM thermal and plasma tools for 3nm and < 3nm nodes.
- Successfully led the transfer of process technology from ASM demo tools to customer onsite.
- Led ASM Tool startups for thermal and plasma metal fleets at customer sites.
- Pioneered the integration of real time sensing for chamber clean and recovery, reducing the tool down time by 30%.
- Developed and implemented new processes with 5% improvement of yield and 10% reduction in defects.
- Root cause, troubleshoot and resolve semiconductor equipment and process issues.
- Develop and maintain process control systems and standard operating procedures (SOPs). Ensure accurate documentation of process parameters, changes, and results.
- Collaborated with hardware/software/sales/BU to optimize equipment performance and troubleshoot process deviations through hardware CIPs.
- Technology Transfer & Scale-Up
Senior Process Engineer I, Corporate Research & Development
ASM International
Leuven, Belgium
05.2022 - 06.2023
- Owned and managed three ALD pilot production tools, maintaining >90% uptime through proactive monitoring and optimization.
- Developed and implemented preventive maintenance (PM) schedules and troubleshooting protocols, reducing unplanned downtime by 30%.
Staff Engineer, Systems Team, cSSD
Micron
Hyderabad, Telangana, India
11.2021 - 10.2022
- Developed high and low temperature reliability check points for SSD memories.
- Orchestrated the successful approaches for performance and reliability studies of NAND memory at various temperatures. Reducing testing time by 30%.
Staff Engineer, Device Team
Western Digital
Bangalore, India
04.2017 - 10.2021
- Led end-to-end reliability and process qualification of legacy 2D NAND technology, supporting high-volume manufacturing (HVM) release through endurance, retention, and stress validation using DOE, SPC, and structured failure analysis methodologies.
- Developed and optimized erase control algorithms to mitigate erase disturb mechanisms, improving process stability, cycling performance, and manufacturing yield.
Education
Ph. D - Centre for Nanoscience and Engineering
Indian Institute of Science
Bangalore, India01-2018
M. Tech - Nanoscience, Centre for Nanoscience and Technology
Anna University
Chennai, Tamilnadu, India01-2011
B. Tech - undefined
YPR college of Engineering, JNTU Hyderabad
AP, India01-2008
Skills
- Material Processing and device fabrication
- Atomic layer deposition of metals and dielectrics
- Chemical vapor deposition of thin films, mainly 2D materials
- Transfer of 2D materials from the grown substrate
- Thermal evaporation, sputtering and etching
- Lithography: e-beam and photo
- Characterization
- Electron microscopy – SEM and EDX
- Raman spectroscopy and photoluminescence
- X-ray photo spectroscopy (XPS)
- Atomic force microscopy
- XRD of polycrystalline/epitaxial films
- Electrical characterization: CV, IV of MOS devices, four probe & Hall measurements
- Others: ImageJ, JMP, Origin, MATLAB, Spotfire, Unix
Accomplishments
- Designed DOE strategy that improved within wafer non-uniformity by 8%.
- Developed standardized troubleshooting guide that reduced MTTR (Mean Time to Repair) by 15%.
- Improved manufacturing yield from 80% to 90% within one year through SPC-driven process control.
Affiliations
Institute of Electrical and Electronics Engineers
Languages
English
Full Professional
Hindi
Full Professional
Telugu
Full Professional
Publications
- V. Kranthi Kumar, Sukanya Dhar, Tanushree H. Choudhury, S. A. Shivashankar and Srinivasan Raghavan, “A Predictive Approach to CVD of Crystalline Layers of TMDs: The Case of MoS2”. Nanoscale, 2015,7, 7802–7810.
- Hareesh Chandrasekar, Krishna Bhardwaj, Kranthi Kumar, Swathi Suman, Navakanta Bhat, Manoj Varma, Srinivasan Raghavan, “Spotting 2-D Atomic Layers on Aluminum Nitride Thin Films” IOP, Nanotechnology, October 2015.
- Sukanya Dhar, V. Kranthi Kumar, Tanushree H. Choudhury, S. A. Shivashankar and Srinivasan Raghavan, “Chemical vapor deposition of MoS2 layers from Mo-S-C-O-H system: thermodynamic modeling and validation”, Physical Chemistry Chemical Physics, 18, 14918-14926, 2016.
- Sukanya Dhar, Anjali Lalithamabika, V. Kranthi Kumar and Srinivasan Raghavan, “Thermodynamic Modeling of W-C-O-H-S system: for controlled growth of WS2 atomic layers by True CVD”, ECS Trans.,77, Issue 2,49-59, 2017.
Patents and trade secrets
- Adaptive erase voltage for reduction in erase time at elevated temperature (US Patent granted - 2020)
- Reducing charge migration in a memory system (US Patent granted - 2022)
- Resuming write operations after suspension (US Patent granted - 2022)
- Memory circuitry and method used in forming memory circuitry (US Patent granted - 2022)
- Selective deposition of metal (US Patent granted - 2022)
- Selective Deposition of Oxide material and deposition assembly (US Patent granted - 2023)
- End point detection of chamber clean (US Patent granted - 2025)
Timeline
Senior Process Engineer I, Metal Logic Team
ASM America
07.2023 - Current
Senior Process Engineer I, Corporate Research & Development
ASM International
05.2022 - 06.2023
Staff Engineer, Systems Team, cSSD
Micron
11.2021 - 10.2022
Staff Engineer, Device Team
Western Digital
04.2017 - 10.2021
M. Tech - Nanoscience, Centre for Nanoscience and Technology
Anna University
B. Tech - undefined
YPR college of Engineering, JNTU Hyderabad
Ph. D - Centre for Nanoscience and Engineering
Indian Institute of Science