Summary
Overview
Work History
Education
Skills
Additional Information
Timeline
Generic

Krishnanjali Damera

New Haven,CT

Summary

Highly motivated and skilled ASIC Verification Engineer with a strong background in System Verilog, UVM, and constrained random testing. Seeking a challenging role within Apple's growing wireless silicon development team to contribute to the development of the next generation of wireless silicon.

Overview

5
5
years of professional experience

Work History

Design Engineering Intern

Silicon Labs
05.2023 - 08.2023
  • Responsible for the AHB2SLAXI shim verification
  • Begin by understanding the IP and SLAXI protocol specifications.
  • In the verification environment, SLAXI components have been replaced with AXI4 components, which may be switched between AXI4 and SLAXI interfaces through a configurable switch.
  • Developed a scoreboard for data integrity testing.
  • Worked together with my superiors and designer to figure out the worst-case scenarios.
  • Written test cases in accordance with the verification plan
  • Enabled the sampling of cover points.

SOC Verification Engineer - Contractor

Advanced Micro Devices, AMD
12.2021 - 07.2022
  • Recognized the complexities of the SOC environment.
  • Block owner for the LPD interconnect, which is one of the complex SOC's five interconnects.
  • A fundamental understanding of the ACE-Lite protocol.
  • Used with perforce commands for the project and Jira for filing the bugs,
  • Excluded the bins in accordance with the Design specifications.
  • Developing directed testcases for functional and code coverage.
  • Analyzing and fixing regression failures.
  • Debugged critical bugs and filed bug in Jira.
  • Cross checked all the corner scenarios.

ASIC Verification Engineer-contractor

Axiado India Pvt. Ltd
06.2021 - 11.2021
  • Point of contact for eMMC block SOC level verification.
  • Created test plan for the eMMC block.
  • Worked with the team to create c testcases for the corresponding blocks using Jira.
  • Enabled the block's code coverage metrics.
  • Worked with IP vendors to resolve VIP bugs.
  • Fixed major roadblocks in the SOC level simulation.
  • Worked with the design team to cover the corner cases.
  • Gained experience with .yml file usage.

Project Engineer

Centre For Development Of Advanced Computing
01.2020 - 05.2021
  • Comprehended the detailed documentation of the AXI4 protocol and the SD protocol.
  • Developed test cases in accordance with the Verification plan and assisted the team in this regard.
  • Created the SD card VIP, i.e., SD slave, because the environment only includes the AXI4 master VIP.
  • Created a scoreboard in UVM and integrated it into the environment.
  • Created a module that aligns valid 32bit data to the LSB.
  • Upon confirmation with my Verification lead, I added test cases to the Verification plan.

SOC Verification Engineer

Chipsolve Technologies India
06.2018 - 12.2019
  • Project - AHB Arbiter SOC level verification June 2019 – Dec 2019
    • Developed Verification environment in System Verilog.
    • Worked with AHB VIP, which can be configured as master or slave.
    • As the DUT supports 4 masters and 4 slaves, Instantiated the VIP with required configuration.
    • Written positive and negative INCR burst test cases.
    • Tested Reset Scenarios
  • Intel Corporation India
    SOC Verification Engineer – Contractor Oct 2018 – May 2019
    • Collaborated closely with the verification leader and development teams to place standard cells.
    • Researched the UPF2.0 format for the Subsystem's low power verification and created a Low power test enter and exit the Low power state.
    • Created the assertion for X-propagation of the block's various output signals.
    • Checked the waveform for the Power-Up and Power-Down sequences.
    • Created assertion to verify the connectivity of tile reset, power enables, and Isolation enable to all IPs in the peri subsystem.
  • Project - AHB2APB Bridge June 2018 - Sept 2018
    • Using System Verilog, Developed the AHB 2 APB IP test bench environment.
    • Developed the AHB master VIP using System Verilog and Memory Slave with APB interface.
    • Developed an AHB protocol coverage plan and coded the cover groups and cover points to ensure that all scenarios are covered. Developed Verification environment for AHB2APB bridge.
    • Connected AHB VIP with the AHB2APB bridge and other end it is connected to memory.
    • Verified all the AHB protocol scenarios, singles and Burst transactions.
    • Developed a sequences and Test scenarios of different kind of Transfers.
    • Developed the Scoreboard to check the AHB and APB transactions.
    • Created coverage plan for AHB protocol and coded the cover groups and cover points to make sure all the scenarios are covered.

Education

Master of Electrical Engineering -

University of New Haven
New Haven, CT
12.2023

Skills

  • Technical Proficiency: Verilog, VHDL, System Verilog, C, UVM, Low power concepts, PERL (Basics), UPF20
  • Methodologies: UVM, UVM-RAL
  • Bus Protocols: AMBA-AHB, AMBA-AXI, AMBA-APB, ACE-Lite (Basics)
  • IP Protocols: Secure Digital (SD) Protocol, eMMC protocol
  • Tools: Synopsys VCS, Questa sim, Verdi, EDA Playground
  • Languages: VHDL, Verilog, System Verilog, C, Low power concepts, PERL (Basics)
  • Operating Systems: Windows and Linux
  • Microsoft Office (Excel, Word, PowerPoint)

Additional Information

  • Knowledge of ASIC verification simulation and testbench development flows with System Verilog and UVM
  • Experience with constrained random testing, coverage closure, and RTL/gate simulations
  • Proficient in scripting with Python, Perl.
  • Familiarity with communication/networking chips
  • Excellent communication and teamwork skills.

Timeline

Design Engineering Intern

Silicon Labs
05.2023 - 08.2023

SOC Verification Engineer - Contractor

Advanced Micro Devices, AMD
12.2021 - 07.2022

ASIC Verification Engineer-contractor

Axiado India Pvt. Ltd
06.2021 - 11.2021

Project Engineer

Centre For Development Of Advanced Computing
01.2020 - 05.2021

SOC Verification Engineer

Chipsolve Technologies India
06.2018 - 12.2019

Master of Electrical Engineering -

University of New Haven

Similar Profiles

CREATE PROFILE
Krishnanjali Damera