Kunal Chhabriya

Peripheral Component Interconnect Express (PCIE)

• Debugged code, troubleshot software, performed root cause analysis and reviewed program quality
• Integrated in house PHY with Root complex pipe macro and End Point MAC environment for running nightly regression tests on PHY
• Worked closely with other development team members to identify and remove software bugs. Coordinated with Application engineers for customer feedback and post-production testing
• Completed exhaustive PCIE training at Mindshare

400G Muxponder(MXP)

• Successfully led traffic bring up for Infinera's Gen4 transponder module which supports 400G of line side bandwidth for up to twenty 10G clients and two 100G clients (from manufacturing phase to installation in chassis)
• Conducted board bring up activities from manufacturing to production phase
• Designed and developed applications in C++ for switch fabric programming to support 10G and 100G services
• Planned and executed unit tests for Data path verification of the entire MXP module. This involved testing QPSK, BPSK and 16 QAM modulation formats for various clients (including 10Gbe, 100Gbe, ODU4 switching and ODU2 switching)
• Provided effective demonstrations to key customers

Enhanced Chassis Replacement(ECR)

• Delivered an exceptional level of service to customer by developing C++ application allowing them to replace their failed chassis in the field by merely changing the node Id (unique identity of chassis) in the newly replaced chassis via CCLI configuration
• Solely unit tested ECR across multiple long haul and metro platforms provided by Infinera

Protection Switching Lead for multiple releases

• Provided essential training pertaining to protection switching and OTN fault propagation protocols to testers and developers involved in the project
• Conducted root cause analysis of all the incoming bugs which led to developers spending less time for debugging issues not belonging to them and testers spending less time on duplicate issues

Lead software developer for protection switching applications

• Built Single and Dual Equipment Protection applications which allows customers to configure work and protect paths for a given 10G or 100G service AND switch to the alternate paths within 50ms in case of service level faults and equipment failures respectively
• Improved debugging times between protected and unprotected issues by at least 25% by developing traffic disruptor tool which allows testers to verify potential switching times on an unsecured service

Optical Test Lead for 100G transponder module

• Planned and executed tests for 100G transponder modules for Integration testing and verification phases of the test cycle
• Automated tests for optical networking protocols namely auto-discovery, automatic gain control and power control loops
• Ensured various modulation formats including QPSK and BPSK work accurately by testing the modulation formats for appropriate Q values (signal to noise ratios)
• Verified system upgrades and data base restores don't impact traffic
• Certified performance across native and subsea link configurations

Firmware testing for Optical Raman Module(ORM)

• Certified Optical Raman Module (EDFA + Raman) for appropriate functionality of DSP with respect to triggering alarms and their propagation to software and management layers.
• Verified gain range for EDFA and RAMAN modules for different fiber types.
•  Automated firmware tests using iTest.

System Verification Tests for 40G transport line module

• Tested 40G line module for auto discovery, alarms propagation, performance monitoring, Transmit and Receive control loops and stress tests.

BCM SDK Testing

• Executed tests involving setting up GMPLS for three node setup and testing L2/L3 functionality. Involved pumping traffic via AUX port and checking if the packet reaches destination appropriately without being flooded to CPU.

Lookup the Database for Switching and Routing Information

• Designed lookup database for different frame formats, providing relevant information for switching/routing the packet. Involved high speed multiple clock domain design
• Database comprised of SRAM and TCAM. All memories supported ECC. Used RTL compiler for synthesis
• Documented design and functional specification for review by various teams within Cisco

Router

• Implemented applications to design and verify three port switch