Summary
Overview
Work History
Education
Skills
Timeline
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LOPAMUDRA SEN

Acton,MA

Summary

Detail-oriented and highly skilled Verification Engineer with strong expertise in digital verification methodologies, including constrained random testing, functional and code coverage, and assertions. Proficient in SystemVerilog, UVM, and scripting languages such as Python and Perl. Demonstrates strong understanding of digital design fundamentals, computer architecture, and communication protocols. Proven ability to work independently and collaboratively to achieve project milestones, with excellent problem-solving and communication skills.

Overview

19
19
years of professional experience

Work History

Senior Staff Engineer

Qualcomm
09.2017 - Current
  • Spearheaded the verification of cutting-edge 5G IP and subsystem components, including signal processing and wireless communication blocks.
  • Developed and maintained UVM-based verification environments for complex, high-throughput digital blocks and subsystems.
  • Defined and executed verification strategies for multiple IP blocks, ensuring high code/functional coverage and robust assertion checks.
  • Led a group of junior engineers in verifying critical 5G subsystem components, assigning tasks, reviewing deliverables, and guiding debug efforts.
  • Acted as a key member of the technical interview panel, actively participating in hiring of full-time engineers, interns, and new graduates.
  • Mentored and onboarded new team members, including interns and new grads, providing structured guidance on company policies, team structures, work processes etc.
  • Collaborated cross-functionally with design, FW,systems, and post-silicon validation teams to ensure timely and high-quality project delivery.
  • Scripted automation flows in Python to streamline regression testing, data analysis, and coverage tracking.
  • Recognized with a special stock award on Dec, 2023 for demonstrating exceptional leadership potential across the entire Modem group.

Lead Verification Engineer

Aricent
08.2016 - 09.2017
  • Memory Controller Verification: IP level verification: The goal of this project is to verify an IP for Intel's 3D Memory Controller. The verification environment is UVM (Unified verification methodology) compliant. The memory interfaces are AMBA AXI protocol compliant. Used UVM Register model for register configuration.
  • Sub system level verification: Integration verification of multiple IPs. Constrained random stimuli generation through multiple interfaces is main challenge for this project. Logic to remove illegal scenarios from the test cases.
  • Awarded with Aricent Kudos for outstanding performance at Intel in April 2017.

Senior ASIC Engineer

SanDisk
01.2015 - 07.2016
  • Assertion Based Verification: I have applied assertion (System verilog assertions (SVA) and property specific language (PSL)) to verify the temporal relation of output signals with respect to inputs.
  • PARAMDEC IP verification: Verification of generate voltage for multistate memory cells from different configurable parameters.

Senior ASIC Engineer

Rockwell Automation India Private Limited
02.2011 - 01.2015
  • Verification of Multiport Ethernet Switch for an SoC: The goal of this project is to verify the functionality of an Ethernet switch. The Switch also supports different communication protocols like DLR, BRP etc. The switch support flow control mechanism. It also supports priority based frame transmission.
  • Verification of NAND Flash Controller: The goal of this project is to verify the functionality of the NAND Flash Controller. Involved in top level verification of the controller along with the boot code sequence verification through an external flash device. Checked the performance of the NAND Flash Controller to meet specific bandwidth of operation at power down.
  • Awarded with outstanding performance recognition certificate from Rockwell Automation for putting exceptional effort in one of the critical controller ASIC Verification on June, 2012.

Verification Engineer

Interra Systems
08.2006 - 02.2011
  • SoC Level Verification: The assignment is to verify the DFT logic used in one of the major SoC in Texas Instruments. DFT logic includes the verification of test pin muxing, connectivity checking, muxed connectivity, pipelined connectivity, clock division. Power domain related checks include isolation, retention of the previous value of Power Domain (PD) ports. All the above verification effort are automated with scripting.
  • IP Level Verification: The goal of this project is to verify the functionality of the EFUSE Controller through Formal Methods.
  • Received “Flamingo Award for Excellent Professional Attitude” for excellent service in Texas Instruments SoC verification project in Oct-09.
  • Awarded with Interra trophy for showing technical excellence and dedication in Formal Verification project for Texas Instruments in 2009.


Education

Bachelor of Science -

College of Engineering And Management, Kolaghat
West Bengal, India
05-2006

Skills

  • Languages: SystemVerilog, Verilog, Python, Perl, C/C, Assembly (basic)
  • Methodologies: UVM, Constrained Random Verification, Assertions, Functional & Code Coverage
  • Tools: Simulation and Debug Tools (eg, VCS, IUS), Coverage Tools
  • Concepts: Digital Logic Design, Computer Architecture, Data Structures & Algorithms
  • Soft Skills: Independent Contributor, Effective Communicator, Team PlayerSytem verilog, UVM

Timeline

Senior Staff Engineer

Qualcomm
09.2017 - Current

Lead Verification Engineer

Aricent
08.2016 - 09.2017

Senior ASIC Engineer

SanDisk
01.2015 - 07.2016

Senior ASIC Engineer

Rockwell Automation India Private Limited
02.2011 - 01.2015

Verification Engineer

Interra Systems
08.2006 - 02.2011

Bachelor of Science -

College of Engineering And Management, Kolaghat

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