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Modified Borrow Select Subtractor For Low Power And Area Efficiency., Xilinx ISE 14.7
This project discusses about architectures of modified borrow select subtractor that consume low power with increased area efficiency. Moreover, I have presented and discussed the modifications carried out in the logical flow of subtraction process by using blocks with lower number of logic gates lead to a smaller number of gates, thus resulting in less device count, lower area and lower power dissipation.
I, Madhusudhan Reddy Kuppam do hereby confirm that the information given above is true to the best of my knowledge.