Mahesh Nerella
Sunnyvale,CA
Summary
Design verification expert with 11 years of experience in verifying multiple complex designs. Detail-oriented in coding and testing the functionality of deliverables.
Overview
11
11
years of professional experience
Work History
Technology Architect
Eximius Design/Wipro
03.2019 - Current
- Successfully verified 5 projects in SystemVerilog - UVM for TPU subsystem team in Google.
- Built a constraint random UVM testbench for a complex subsytem that has NIC 400, dual core CPU, multiple DMA's, MMU and other proprietary blocks.
- Responsible for verifying AXI datapath's.
- Full ownership of CSR verification using RAL.
- Full ownership of verifying CPU Debug paths CTI, ATB interfaces.
- Involved in verifying Mailbox blocks.
- Verified DVFS, Powergating and clock gating sequence.
- Driven functional and toggle coverage closure.
Engineer, Senior
Qualcomm Inc
04.2018 - 03.2019
- Responsible for block level verification of CPR(Core Power Reduction).
- Developed CPRF and CPRC Verification TB from Scratch
- Responsible for test-plan to coverage closure.
- Developing sequences (.seq files) and drivers that will be used at SS and SOC teams
- Support to SS, SOC and testchip teams for multiple projects.
Senior Verification Engineer
Mirafra Software Technologies Pvt Ltd
08.2015 - 09.2017
- Successfully verified IP level and testchip verification for multiple projects for Qualcomm.
- Responsible for block level verification of CPR(Core Power Reduction).
- Developed CPRF and CPRC Verification TB from Scratch
- Responsible for test-plan to coverage closure.
- Developing sequences (.seq files) and drivers that will be used at SS and SOC teams
- Support to SS, SOC and testchip teams for multiple projects.
- Verified Multiple test chips, TestBench Bring-up, Toggle coverage closure. Verified different blocks in each chip.
Senior Engineer
Synapse Techno Design Innovation Pvt Ltd
07.2012 - 07.2015
- Worked multiple projects for ADI and TI.
- Responsible for block level verification of configurable USART for TI. Developed test planning, TB bringup in system verilog-UVM from scratch, programming sequence and test case, RAL and coverage closure.
- Part of subsystem level verification team in ADI, Handled SPI, OTP and test bus block, Verified Error matrix, programming Testcases, Assertions. Modeled Functional Coverage and driven Coverage Closure includes code and
functional, Executing regressions of multiple blocks.
Education
B.Tech -
SRM University
Chennai2011
Intermediate -
SKVS Junior College
Vijayawada2007
Secondary School Certificate -
Bhasyam Public School
Guntur05.2005
SSC -
Board of Intermediate Education
2005
Skills
- Excellent experience in verifying complex subsystems with AXI data paths between multi core CPU, DMA's, NIC and memories
- Excellent experience in bringing up complex TestBench in System Verilog - UVM in block level and subsystem level
- Test Planning, programming test cases, sequences, assertions Modeled Functional Coverage and driven Coverage Closure includes code and functional, Executing regressions
- Constrained Randomization
- CSR verification using RAL
- Experience in on chip bus protocols like AXI, AHB and APB, other company specific propraitory protocols
- Experience in serial protocols like UART, SPI, I2C
- Experience in DVFS, APG and ACG verification
- Verifying BISR paths, CPU debug path's like ATB and CTI
Timeline
Technology Architect
Eximius Design/Wipro
03.2019 - Current
Engineer, Senior
Qualcomm Inc
04.2018 - 03.2019
Senior Verification Engineer
Mirafra Software Technologies Pvt Ltd
08.2015 - 09.2017
Senior Engineer
Synapse Techno Design Innovation Pvt Ltd
07.2012 - 07.2015
B.Tech -
SRM University
Intermediate -
SKVS Junior College
Secondary School Certificate -
Bhasyam Public School
SSC -
Board of Intermediate Education
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