Manoj Parameswaran
Chandler,AZ
Summary
- 22 years of experience in ASIC design and implementation
- Strong blend of technical expertise and team management skills.
- Hands-on experience in various aspects of the semiconductor lifecycle
- SoC integration, IP design, subsystem microarchitecture, SoC and IP verification, pre-silicon validation, CDC, synthesis, STA, power analysis, clock tree synthesis, and timing closure.
- Diverse domains - automotive, IoT, medical, and wireless domains.
- Part of multiple tapeouts adhering to schedule, power, area, and timing requirements.
Overview
22
22
years of professional experience
Work History
Senior Technical Staff Engineer/Manager
Microchip Technology Inc
01.2018 - Current
SoC Design Integration for the SAM series (ARM based) Microchip MPUs.
Manage design and verification teams spread across Chandler, Chennai and Cambridge
Part of 5 SoC developments
Microarchitecture/ IP Integration / IP Vendor Interfacing / Architecture Exploration
Team Building – US/India - Recruitment, Rampup
Verification methodology improvement initiatives
Senior Architect - Product Engineering Services
Wipro Technologies
05.2005 - 01.2018
SoC Design Consultant
SoC Design Integration, Verification and Static Timing Analysis for multiple customers (Intel, TI, HP)
Customer point of contact for Design development
IP Design and Verification
Junior Research Fellow - Hardware Design Group
C-DAC
03.2003 - 04.2005
Embedded Solar battery charger - Firmware and board design
Education
B.Tech - Electronics and Communication
Government College of Engineering
Kannur, Kerala01.2001
Skills
- ARM Based System On Chip Design
- SoC Verification Expertise
- IP Integration Expertise
- MIPI DSI/CSI/DPHY Expertise
- Collaborative Team Development
- Team Management
Websites
EDA Tools
- Spyglass Lint
- Questa CDC
- Synopsys DC
- Synopsys Primetime
- Cadence Jaspergold - FPV, Connectivity
- Cadence Xcelium, Synopsys VCS, Siemens Questasim
Personal Information
Nationality: India
Achievements And Publications
DAC 2011 – User Track: 'An Automated Methodology for Creating Complex SOC Derivatives', Hari Pendurty, Manoj Parameswaran, Midhun Chandran
Timeline
Senior Technical Staff Engineer/Manager
Microchip Technology Inc
01.2018 - Current
Senior Architect - Product Engineering Services
Wipro Technologies
05.2005 - 01.2018
Junior Research Fellow - Hardware Design Group
C-DAC
03.2003 - 04.2005
B.Tech - Electronics and Communication
Government College of Engineering
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