Manzurul Khan
San Jose,CA
Summary
20+ years experience in EDA software development. 8+ years experience in FPGA prototyping tool development. Strong background in STA module. Looking for a challenging position in software development.
Overview
27
27
years of professional experience
Work History
Software Architect
Cadence Design System
Santa Clara, CA
12.2018 - Current
- Working as a lead software developer for STA module in internal FPGA prototyping tool.
- Lead a team of sofware engineers to develop a FPGA Timing Model based STA engine for fast compile during system-level timing analysis.
- Enhanced FPGA Timing Model to support distributed TDM scheduling.
- Enhanced FPGA timing model to support timing-driven global router.
- Developed a physical pin-based SLR delay compensation module in STA to aid PNR.
- Worked with the DCALC team to integrate Xilinx load-based WLM in STA.
Sr R&D engineer
Synplicity/Synopsys Inc.
Mountain View, CA
02.2008 - 11.2018
- Worked as a developer for PrimeTime (Static Timing Analysis Tool).
- Owned UPF (Unified Power Format) module of the engine.
- Designed and implemented new UPF flow to automatically generate UPF connectivity from verilog.
- Enhanced different PT flow including hierarchical timing, ETM, ECO for UPF.
- Developed UPF writer for bottom-up hierarchical timing flow.
- Implemented disk save/restore for UPF data structure.
- Worked as a software developer for FPGA prototyping platform.
- Integrated Xilinx Timing Models with Static Timing Engine used by the compiler.
- Fixed issues in Timing Constraints and Constraint Checker.
Member of Technical Staff
Sun Microsystem, Inc.
Santa Clara, CA
12.2001 - 02.2008
- Worked as a developer for Static Timing Analysis(STA) tool to support the need of the in-house 16 core microprocessor design.
- Designed and Implemented Donut Model for hierarchical timing which involves creating models of the sub graphs that can be used in higher level timing graph for faster run.
- Implemented Reverse Donut Model for hierarchical timing which involves creating a model of superset graph that can be used in lower level run. Own a patent for this.
Design Engineer
Xenon InfoTech
Edison, NJ
09.2001 - 12.2001
- Provided support for EDA tools and flows.
Design Engineer
Metaflow Technology/STMicroElectronics
San Diego, CA
06.2000 - 08.2001
- Worked as an emulation engineer.
- Successfully detected bugs that caused the keyboard malfunction and command malfunction. Created the bugs in the RTL simulation environment. RTL designers were able to fix those bugs and make the design working.
Assistant Engineer
Haroon Groups
Dhaka, Bangladesh
01.1998 - 12.1998
- Worked as QA engineer in assembly line.
Education
MSc - Electrical Engineering
Colorado State University
Fort Collins, CO, USA06.2000
BSc - Electrical Engineering
Bangladesh University of Engineering and Technology
Dhaka, Bangladesh06.1997
Skills
- Static timing analysis
- Timing model generation
- Hierarchical timing methods
- Cross-functional team leadership
- Distributed System
- Machine Learning
- Progamming in C/C, Python
Accomplishments
- Hold Patent on Reverse Donut model(US7849430)
- Cadence Internal Innovation conference 2022: Presented FPGA Timing Model based STA engine for system level timing analysis.
- Cadence Mini MBA: Completed Performance Leader Program from Berkley Haas School of Business.
Timeline
Software Architect
Cadence Design System
12.2018 - Current
Sr R&D engineer
Synplicity/Synopsys Inc.
02.2008 - 11.2018
Member of Technical Staff
Sun Microsystem, Inc.
12.2001 - 02.2008
Design Engineer
Xenon InfoTech
09.2001 - 12.2001
Design Engineer
Metaflow Technology/STMicroElectronics
06.2000 - 08.2001
Assistant Engineer
Haroon Groups
01.1998 - 12.1998
MSc - Electrical Engineering
Colorado State University
BSc - Electrical Engineering
Bangladesh University of Engineering and Technology
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