Summary
Overview
Work History
Education
Skills
Relevant Coursework
Accomplishments
Timeline
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Marilyn Vazquez

San Jose,CA

Summary

Validation Engineer with 2 years of experience testing and qualifying network hardware across multiple product generations, including NVIDIA B200/CX7, B300/CX8, BlueField-3, and Supermicro NIC platforms spanning Intel, Broadcom, and Mellanox silicon. Collaborate cross-functionally with hardware, network, and systems teams to validate IPMI/BMC and NIC functionality at scale. Filed 100+ defects across projects, the highest issue discovery rate on the team, directly improving product quality before release. Eager to take on deeper hardware engineering challenges.

Overview

4
4
years of professional experience

Work History

Validation Engineer

Supermicro
11.2023 - Current
  • Validated pre-release NVIDIA ConnectX-8, ConnectX-7, and BlueField-3 adapters in InfiniBand and Ethernet environments, performing RDMA benchmarking and latency testing using iperf, ib_send_bw, ib_write_bw, and ib_read_lat
  • Executed multi-SKU NIC validation across Intel and Mellanox/NVIDIA Supermicro platforms, covering SR-IOV, VLAN, EEPROM firmware, OS interoperability, and performance testing
  • Validated 400G and 800G transceivers and fiber optic cabling in high-performance networking environments using Quantum-X800 InfiniBand switches
  • Performed IPMI/BMC firmware regression and WebGUI functionality testing across Supermicro motherboard platforms using automated test suites and stress testing
  • Developed and adapted Bash scripts and SOPs to streamline validation workflows and support peer onboarding
  • Filed 100+ defects across projects, the highest issue discovery rate on the team, directly improving product quality before release
  • Regularly called upon to provide cross-team support for network and systems teams alongside primary project work

IT Systems Administrator I

Synopsys Inc
06.2022 - 08.2022
  • Provisioned and configured systems for new users, ensuring hardware and software readiness prior to deployment
  • Provided Tier 2 and Tier 3 technical support, diagnosing and resolving hardware and software issues for internal employees
  • Configured and tested Windows Server OS with roles and features

Education

Bachelor of Science - Computer Engineering

San Francisco State University
San Francisco, CA
05.2023

Skills

  • NVIDIA Tools - Nvnetperf NVQual, Doca
  • Test Plan Execution,
  • Test Report Writing
  • Spanish Speaker
  • Ethernet/Infiniband
  • Ubuntu/RHEL

Relevant Coursework

 Microelectronics:

  • Measured the characteristics of standard electronic devices (diodes, BJTs, FETs, op-amps) and compared them to LTspice simulations.
  • Produced technical reports with data analysis, plots, and interpretation.

Digital System's Design with Verilog:

  • Analyzed/Designed combinational and sequential circuits using various modeling methods
  • Employed HDL for circuit design/simulation, including structural, dataflow, and behavioral approaches

Design with Microprocessors with C and Keil Uvision: 

  • Proficient in microprocessor/microcontroller architecture
  • Interfaced with memory and I/O devices, utilized timer, counter functions, interrupts

Operational Amplifier Systems Design with SPICE:

  • Explored resistive op-amp circuits, emphasizing feedback principles
  • Designed and evaluated active filters, studied op-amp and comparator applications in testing, control, and instrumentation

Accomplishments

    Senior Capstone - Performance Tracking Rowing Machine:

  • Collaborated in a three-member team to create the "Performance Tracking Rowing Machine Website"
  • Designed and added a device for real-time performance feedback on rowing machines
  • Integrated rotary encoders, load cells, ESP32, and Arduino components
  • Developed a user-friendly webpage interface to track metrics like distance, speed, and force distribution
  • Scoreboard Controller:

  • Designed and executed FPGA-based sequential designs for controlling a two-digit decimal score on two seven-segment displays
  • Incorporated functionality to increment the score by 1 or 10 through user input from pushbutton switches
  • Included a reset button to clear the score to zero
  • Addressed specifications including switch debouncing, clock division, and correct display refresh rates

Timeline

Validation Engineer

Supermicro
11.2023 - Current

IT Systems Administrator I

Synopsys Inc
06.2022 - 08.2022

Bachelor of Science - Computer Engineering

San Francisco State University