Summary
Overview
Work History
Education
Skills
Publications
Timeline
Generic

MARIO COP

Seattle,WA

Summary

Engineering professional with proven ability to innovate and solve complex technical challenges. Known for delivering high-quality solutions and driving team success through effective collaboration and adaptability. Skills include systems analysis, project management, and technical troubleshooting.

Overview

4
4
years of professional experience

Work History

Senior Semiconductor Engineer

IOActive
01.2024 - 02.2025
  • Performed sample preparation, optical inspection, material deconstruction, leveraging precision delayering, chemical etching, and Focused Ion Beam milling to analyze semiconductor defects and structures.
  • Developed and optimized methodologies for semiconductor and component-level deprocessing, delayering, and imaging for security-focused reverse engineering.
  • Identified lab safety hazards and procedural gaps, developing EHS protocols and documentation for both technical and non-technical audiences.
  • Owned tool installation and maintenance, managing consumables and servicing for dual ion beam systems, polishing tools, and wet lab chemicals.
  • Managed lab operations, maintaining equipment and standard operating procedures (SOPs) for increased effectiveness and scalability.
  • Conducted microprocessor netlist and flash extractions using third-party software to analyze product security vulnerabilities and component behavior.

Failure Analysis R&D Engineer

Intel Corporation
09.2020 - 01.2024
  • Led and managed customer-focused and exploratory projects (projects included but not limited too within the semiconductor landscape, ensuring satisfaction through collaboration with cross-functional teams to deliver critical analysis and insights.
  • Performed physical failure analysis through sample preparation, delayering, and de-processing using polishing, wet/dry etch, and Focused Ion Beam (FIB) assisted techniques.
  • Analyzed packaged and unpackaged semiconductor products from multi-die packages and interconnect structures to assess processing, layout, performance, and reliability.
  • Worked from and developed on technical documents, design layouts, and written best-known methods (BKMs) to complete tasks within the desired scope.
  • Knowledge of process flow specifics of silicon wafer processors from silicon to wafer; troubleshooting on the job tasks while ensuring company/customer satisfaction.
  • Managed chemical wet lab operations, ensuring compliance with federal and state regulations.

Education

Bachelors of Science - Chemistry

University of California, Merced

Masters of Science - Materials Science and Engineering

Portland State University

Skills

  • Semiconductor Processes: Semiconductor Manufacturing Proceses (Fab and Failure Analysis), DOEs, and Statistical Process Control (SPC)
  • Documentation: Technical writing, training guides, process documentation, and laboratory management
  • Soft Skills: Project management/planning, customer interactions
  • Material Testing/ Material Characterization: Electromechanical Inspection of semiconductor devices using tools such as (not limited too) Scanning Electron Microscope, Focused Ion Beam, Energy Dispersion Xray Spectroscopy, and FT-IR

Publications

“Extraction of Secrets from 40nm CMOS Gate Dielectric Breakdown Antifuses by FIB Passive Voltage Contrast”, Submitted to USENIX Security, 2025 – pending “peer-review”

Timeline

Senior Semiconductor Engineer

IOActive
01.2024 - 02.2025

Failure Analysis R&D Engineer

Intel Corporation
09.2020 - 01.2024

Bachelors of Science - Chemistry

University of California, Merced

Masters of Science - Materials Science and Engineering

Portland State University

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