Mario Evaldo Arenas Macias

Driven by over 14 years of experience in the Electronic industry, with a specific focus on Automotive Powertrain, Hi-Fi Audio systems, High-performance computing systems, and Digital cockpit electronics, I am an accomplished Engineering Leader. I am dedicated to fostering team success by exemplifying a strong work ethic, consistently delivering top-quality results, and demonstrating a clear understanding of company goals. Committed to personal and professional growth, I am motivated to continually expand my knowledge and excel within the electronic industry.

Read science books or fiction novels, DIY Arduino and FPGA projects, Play video games

Visteon Corporation:

• Office startup activity for engineering execution. Defined needs of Hardware Development group in Queretaro. Recruiting a +40 engineers team in less than a year after arrival.
• Support local team with high management sponsorship to develop Intellectual property. Resulting in a new global accountable skill located in Mexico and a ASIC development .
• Coordinate +14 projects running in parallel supporting supervisors to coordinate activities avoiding overload of people.
• Implementation of multiple workarounds to remove roadblocks during Covid19 crisis, avoiding a reduction of the effectivity and efficiency of the operation.
• Brand ambassador, extending Visteon importance across universities, leading efforts to exchange knowledge synergy.
• Develop technical path plans for each engineer in the group.
• Develop a group mindset for accountable and proactive engineering execution.

Harman International

• VAVE savings identification and implementation achieving up to $10M for 3 products for 2 customers (Toyota/GM).
• Main contributor and leader to identify root cause and counter measures to solve GR1 escalation issues with Toyota.
• Implementation of a BOM tool to check and verify discrepancies between manufacturing releases and Schematic BOM.
• Definition of Global process for HW design activities such as Schematic release, validation, bench testing, HW/SW interactions.
• Global process owner and trainer for DFMEA. I've developed and release the DFMEA flow diagram for execution and compliance of the task.
• Development of a HiFi Audio Amplifier class H in a FPGA presented as a possible solution for unbranded audio.
• Owner of the first HW program to do "DV and done" based on the early identification of failures and quick response coordinating the cross-functional team to support and identify failures.
• Low cost FPGA development for high performance power supply to provide a Class-H solution to a current amplifier architecture.

Intel Co.

• Implementation of new debug interface for a high performance PCI graphics card.
• Achieving of platform power ON without blue-wires
• Quick resolution by implementing quality tools
• The project that was developed can be foun the commercial site of intel: https://www.intel.la/content/www/xl/es/products/servers/accelerators.html
• As a HW tech lead I've coordinated the validation team in Taiwan to complete validation in time and review and approve results.
• Suport CPLD solution for platform sequencing development.

Continental

• Development of a new and automated 4x4 ECU bench test to improve warranty return analysis time.
• Development of a DFSS project, achieving $500K in savings by implementig new test excecutions in the testplans.
• Reduction of warranty returns internal and external, by implementing new test and auditing current processes.
• Bench prototype development of a quasi-resonant power supply.