Meline Petrosyan

Experience in design of high-performance and high-speed Analog and Mixed design circuits (GHz)

Experience in full-custom layout and physical verification of high-speed SerDes circuits, including PCIe 6.0 / PCIe 7.0 interfaces, VSR, and XSR architectures, across multiple advanced process nodes.

Major Projects: FOUNDRIES: TSMC, SAMSUNG, GF, INTEL TECH NODES: 2nm, 3nm, 4nm, 5nm, 6nm, 7nm

Actively involved in both transistor-level layout and design-level analysis of analog and mixed-signal IPs, with strong focus on physical verification flows, including DRC, LVS, PERC and EM/IR sign-off. Worked closely with circuit designers to ensure optimal layout floorplanning, symmetry, matching, and parasitic-aware design closure.

Over 4 years of hands-on experience in layout design and verification of SRAM embedded memories, as well as analog and mixed-signal structures across advanced process nodes including CMOS, FinFET, and GAA technologies.

Experience in all aspects of layout design, starting with the concept, through all phases of physical layout design implementations, strategies, and verifications ( LVS, DRC, ERC, PERC, DFM, Antenna Checks, etc.)

Solid experience in techniques of custom layout floorplanning, hierarchical layout planning, and routing (device matching, isolation/shielding, ESD and Latch-up protection, avoidance of EM/IR)

Sound knowledge of memory compilers, multiple abutment methodology

Experience in design of high-performance and high-speed circuits (GHz)

Strong leadership, troubleshooting, and communication skills

Ability to learn new methodologies/techniques/flows and technologies/processes very quickly

Major Projects: FOUNDRIES: TSMC, SAMSUNG, GF, INTEL TECH NODES: 3nm, 4nm, 5nm, 7nm, 14nm, 22nm, 18A(intel RibbonFET)