Michael Azzaro
Portland,OR
Summary
Highly skilled and detail-oriented engineer with 5 years of experience in process and sort/test development for semiconductor manufacturing at Intel Corporation. Proven expertise in developing and transferring robust and cost-efficient processes. Strong track record of project ownership from NPI to successful technology transfer. Ability to manage multiple projects simultaneously while meeting deadlines. Adept at problem-solving, troubleshooting and collaborating with cross-functional teams to deliver innovative solutions.
Overview
5
5
years of professional experience
Work History
Module/Test Development Engineer
Intel Corporation
08.2021 - Current
- Led development of two first-of-kind probe technologies for novel wafer sort solutions on Intel Lunar Lake and 18A products
- Carried out development from fundamental probe characterization to technology qualification and transfer to HVM including state-of-the-art hybrid bond technology
- Developed strategies for probe assessments including force/mechanical evaluations, current carrying capacity studies, imaging/composition data collection (SEM) and sort performance analysis using statistical methods
- Coordinated collaborative DOEs across modules and product engineering teams to support hybrid bond technology development and solve complex sort process-related issues. Worked with stakeholders on project progress updates and delivered detailed reports on testing activities on a weekly cadence
- Extensive experience and training using and troubleshooting TEL Precio and Prexa platforms for wafer sort recipe creation
- Compiled detailed technical transfer and training documentation from qualified probe technology to support product transfer from development to HVM
Process Development Engineer
Intel Corporation
06.2019 - 08.2021
- Aided in the development of 10nm and 7nm lower layer copper polish process and Copy Exactly transfer to HVM factories
- Responsible for process conversion of 10nm and 7nm to new polisher toolset and new tool qualification
- Module representative for 10 and 7nm Metals Focus Teams - coordinate and support integrated process development through inter-module design of experiments and communication of data on a daily cadence
- Oversaw DOEs to reduce impact of weekly PMs on Manufacturing Availability (MA) and test wafer consumption of resulting in in ~3% MA savings per week
- Inline Metrology Tracking (IMT) representative with goal to reduce defects and improve matching across HVM factories and determine root cause for fab-to-fab mismatches. Developed new dryer process for IMT directive for defect reduction resulting in ~30% defect reduction
Education
Ph.D. - Physical Chemistry
University of Texas At Austin
Austin, TX05.2019
Bachelor of Science - Chemistry
State University of New York At Geneseo
Geneseo, NY05.2013
Skills
- Statistical Process Control
- Process Development/Hardening
- Design of Experiments
- JMP
- Data Analysis/Modeling
- Project Management/Planning
- Failure Modes and Effects Analysis
- Manufacturing Processes
Timeline
Module/Test Development Engineer
Intel Corporation
08.2021 - Current
Process Development Engineer
Intel Corporation
06.2019 - 08.2021
Ph.D. - Physical Chemistry
University of Texas At Austin
Bachelor of Science - Chemistry
State University of New York At Geneseo
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