Mingyi Wang

I will be at this position in the summer of 2024. The following is from the job description:

• You will focus on the performance and manufacturability of Micron's cutting-edge next-generation memories. The role will perform technology integration activities in enabling manufacturability of state-of-art 3D DRAM technology, working on device component such as charge storage devices, thin-film transistors.

Working with onsemi Technology Development (ONTD) team for next generations of power electronics:

• Actively engaged in collaborative projects with the ONTD team, focusing on the development and innovation of cutting-edge power electronics for future applications.
• Played a supportive role in interdisciplinary teams, contributing to the advancement of technology in high-voltage power applications.
• Utilized Sentaurus TCAD for sophisticated modeling of the fabrication process (sprocess) of Trench FETs, a critical component in high-voltage gate driver applications.
• Expertly simulated device performance (sdevice), effectively bridging the gap between theoretical design and practical implementation.
• Conducted comprehensive electrical characterization of HV MOS capacitors, providing vital data for the improvement of device reliability and efficiency.
• Demonstrated proficiency in analyzing and interpreting complex electrical properties, contributing to enhanced device performance.
• Spearheaded doping engineering processes for Trench-FETs, optimizing their electrical properties and performance.
• This initiative played a crucial role in refining device functionality and meeting stringent industry standards.
• Achieved the high performance for Trench-FET in our TCAD deck, compatible with VLSI standards.
• Successfully pushed device performance beyond the projected next-generation roadmap by simulation.

Developing systematic framework for 2D Tellurene Thin-Film Transistors (TFTs):

• Successfully demonstrated the first doping-free CMOS device based on Tellurene
• Operated Atomic Layer Deposition (ALD) of high-k dielectric materials to optimize the device performance
• Utilized Electron-Beam Physical Vapor Deposition to deposit metal electrodes
• Conducted effective annealing methods to optimize the TFT devices
• Performed E-beam Lithography (EBL) for nano-scale devices fabrication
• Performed X-Ray Diffraction (XRD) and analyzed data for Te thin film stack
• Analyzed data of X-Ray photoelectron spectroscopy to study surface chemistry of Tellurene
• Developed a sandwich transport model specifically for Tellurene devices
• The proposed model has been recognized as a generalized approach applicable to most other 2D transistors
• Conducted device simulations utilizing TCAD and compact models, e.g. Schottky Barrier Field-effect Transistors (SB-FET) models
• Finished coding for compact models (Both Python and MatLab)
• Bondless contact engineering for 2D tellurene (PdTe2-Te contact)
• Fabrication of quantum Josephson junction based on Tellurene
• Collaboration groups: Peide Ye (PU), Dana Weinstein (PU), Gary Cheng (PU), Juejun Hu (MIT), and Albert Chiou (NTU-Taiwan)

Working with Prof. G. Jeffery Snyder on thermoelectric, flexible thermoelectric, piezoresistive polymer composites etc.

• Design and fabricated the thermoelectrical (TE) stage for flexible TE nanowires
• Synthesized TE nanoparticles for SPS technology
• Conducted basic nanomaterials characterizations