Summary
Overview
Work History
Education
Skills
Timeline
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Mohamed Mustufa Memon

Cedar Park,TX

Summary

14+ years of experience as a Silicon Physical Design Engineer with a focus on synthesis, APR, and timing signoff for mixed-signal IPs, GPUs, and high-speed CPUs, as well as custom silicon at Intel (14nm, 10nm), TSMC (7nm, 3nm), and Samsung (5nm, 4nm).

Proven success in meeting design deadlines at few different design powerhouses, and now seeking for a managerial/lead position in Physical Design Implementation.

Overview

14
14
years of professional experience

Work History

Silicon Physical Design Engineer

Meta
Austin , TX
04.2021 - Current
  • Led a small team of engineers to implement the physical design of Meta's proprietary security IP for multiple AR/VR custom SoC programs at Meta RL at Samsung 4nm; TSMC 3nm.
  • Assessed and validated multiple third-party IPs from different vendors and open-source forums for security protocols.
  • Owned the complete aspect of design convergence in terms of timing, floorplan, routing, clocks, low power UPF, timing constraints, performance, and power.
  • Physical design flow deployment and development across different tech nodes.
  • Tech node evaluation for future projects.

Sr 2 Apps Consultant

Synopsys
Austin, TX
05.2018 - 04.2021
  • Flow and Methodology Development for High speed CPU Core at Samsung Austin. (Nodes 8 nm, 7 nm, and 5 nm)
  • Worked very closely with the Physical Implementation Team at Samsung Austin (SARC) to develop and deploy new technologies for High-Speed Core CPU designs [Lion (8nm) and Grizzly (7nm)] using ICC2 and Fusion Compiler tools from synthesis all the way through route optimization.
  • Key contributor for CCD-Everywhere flow deployed on the Mesh-Based Designs across all the 10 blocks using a fine-grained library for clock ICGs and clock buffers, which resulted in the replacement of an archaic in-house useful skew flow that led to 20-25% savings on runtime and achieved better PPA across the board.
  • Flow and methodology development for high-speed hierarchical ARM CPU core at the 5nm node.
  • Developed a brand-new top-down and bottoms-up flow to implement a 5 LPE process-based ARMv9 CPU core design hierarchically for the first time at ARM Austin.

Senior Design Engineer

Xilinx Inc
San Jose, CA
07.2016 - 05.2018
  • Senior Design Engineer. (7 nm Project Everest)
  • Physical Design Lead for RTL to GDS for DDR memory controller (two partitions and top-level integration).
  • Block-level implementation: DC constraints, Init, fish tail, CDC, LEC, floorplanning, and PNR (ICC2) using Lynx flow, CTS, extraction using STAR RC, and timing using PT-STA.
  • Top-level implementation: full IP integration, timing sign-off, collateral generation, and delivery to SOC in the form of timing libs for different PVT corners.

High Speed IO Design Engineer

Intel Corporation
Folsom, CA
10.2014 - 06.2016
  • Physical Design implementation of chassis unit for UniPHY SerDes PCIE3 IP on 10 nm process.
  • Collaborated with IP integration team for seamless bottom-up integration of FUB into top-level IP, achieving compliance with all DRC specifications.
  • Executed timing signoff for high-speed serial IO interface with nearly 7,000 pins across 25 distinct clocks in 10 nm technology.
  • Delivered high-quality library files for 12 PVT corners to client SOC team on schedule throughout project lifecycle.

Component Design Engineer

Intel Corporation
Folsom, CA
06.2011 - 10.2014
  • Block Owner for Slice Common in GPU, overseeing section timing verification.
  • Managed multiple blocks for logic synthesis, data path re-timing, and floor planning.
  • Executed place and route (APR), clock tree synthesis (CTS), and timing convergence processes effectively.
  • Addressed functional bugs and setup/design rule violations through challenging engineering change orders (ECOs).
  • Collaborated with mask designers globally to resolve DRC violations across seven partitions.

Education

Masters in Electrical Engineering - Electrical Engineering

University of Southern California
Los Angeles, CA
05.2011

Bachelors in Electronics and Telecommunication -

TSEC , Mumbai University
Mumbai, India
05.2009

Skills

  • RTL2GDS flow specialist
  • Physical design implementation and flow development
  • Timing analysis and static timing analysis
  • Scripting automation and tool debugging
  • EDA tool proficiency
  • Tech node evaluation
  • Vendor Management

Timeline

Silicon Physical Design Engineer

Meta
04.2021 - Current

Sr 2 Apps Consultant

Synopsys
05.2018 - 04.2021

Senior Design Engineer

Xilinx Inc
07.2016 - 05.2018

High Speed IO Design Engineer

Intel Corporation
10.2014 - 06.2016

Component Design Engineer

Intel Corporation
06.2011 - 10.2014

Masters in Electrical Engineering - Electrical Engineering

University of Southern California

Bachelors in Electronics and Telecommunication -

TSEC , Mumbai University

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