Nagendra Angara

Project: Intel Server and CPU projects.

Key Responsibilities and Achievements.

• Performing emulations and simulations to validate RTL SCAN patterns to ensure correctness.
• Partnered with the design team to rigorously analyze and validate internal scan signals, ensuring accurate data and frequencies.
• Converted high-quality patterns to tester formats and prepared comprehensive pattern lists, conducting thorough checklist reviews before delivery.
• Content Enablement (Si bring up) and debugged SCAN vector failures to identify root causes.
• Developed robust test programs for scan modules and performed audits before silicon arrival, achieving 98% and 100% in first-time right patterns (FTRP).
• Fostered a continuous improvement culture in debugging, resulting in over 98% yield across various conditions, meeting project goals.
• Mentored junior engineers to enhance deployment and operations efficiency.
• Drafted clear technical documentation and shared insights with the team.
• Tracked daily team scan activities, providing timely updates and status to support cross-team collaboration.

Project: Clape series, Burma, Lume, and Loki PMIC Silicon bring up Test Case development.

Roles and Responsibilities :

• Optimized Test Programs: Achieved significant reductions in test times for Calpe and Calpe-Large PMIC devices, lowering times from 38s to 13s (65% savings) and from 41s to 12.4s (70% savings) through the implementation of advanced methodologies such as PSET invoking and pattern-oriented programming (POP).
• Ensured Program Stability: Validated and verified test program stability by conducting thorough repeatability tests and Gauge R&R analysis, ensuring high reliability and performance.
• Cross-Group Integration: Successfully integrated programs across multiple teams using version control tools like SVN and GitHub.
• Efficient Test Case Development: Designed and validated robust test cases for Buck, Boost, and LDO modules of DC-DC converters at both wafer sort and FT package levels, contributing to comprehensive product quality.
• Test Pattern Generation: Generated precise test patterns by analyzing device register maps and leveraging customer-specific ATPG scripts to enhance testing accuracy.
• Critical Test Debugging: Diagnosed and resolved critical issues in Buck, Boost, and LDO modules, ensuring optimal performance of test programs.
• Collaboration on Correlation: Actively engaged in Bench to ATE correlation efforts, working closely with chip design engineers to address and resolve correlation issues.
• Automation: Developed an innovative VBA script to identify and reduce wait times within test patterns, resulting in a 40% reduction in overall test time.

Project: Automotive ASIC test program sustaining support.

Roles and Responsibilities:

• Conducted Spike and Plausibility Checks for automotive devices to ensure reliability.
• Modified and Validated Production Test Programs per PCMS, incorporating new tests and adjusting parameters for optimal performance.
• Provided technical expertise in test failure analysis, driving yield improvements.
• Trained technicians and operators on test hardware and software, boosting team efficiency.
• Reviewed test plans to ensure comprehensive coverage of datasheet requirements.

Project: Stoney Ridge APU SoC, Conversion from Verigy V9300 to Sapphire.

Roles and Responsibilities:

• Test Program Development: Created test programs by transitioning from the Verigy V9300 platform to the Sapphire tester platform, ensuring compatibility and performance.
• Automation Development: Developed a Perl script to convert level and timing parameters, and a VBA script for yield report generation, reducing manual effort from 2 hours to just 5 minutes with improved accuracy.
• Data Analysis: Analyzed test results and prepared detailed reports comparing outcomes with the legacy V9300 program, providing insights for optimization.