Namsung Kim

Silicon Technology and Supply Chain Management:

• Leading team of over 50 employees.
• Responsible for cutting-edge logic/memory, advanced packaging (+OSAT), and power electronics.
• Managed entire component Supply Chain Management organization, supporting Tesla products.
• Collaborated on custom System-on-Chips (SOCs) for Autopilot and DOJO supercomputing platforms.
• Overseeing advanced logic process prototyping, custom silicon engineering, library development, vendor qualification, and IP development.

Electronic Supply Chain Optimization:

• Ensured quality and reliability of semiconductor components, integrated circuits, and electromechanical parts.
• Collaborated with engineers, negotiators, data scientists, and program managers to optimize supplier partnerships.
• Managed multi-billion-dollar annual spending.
• Implementing silicon technology and supply sourcing strategies to enhance productivity and streamline operations.

Customer Engagement and Business Opportunities:

• Led and managed multiple customer engagement programs for key customers (Tier 1 foundry & memory).
• Successfully drove future business opportunities (> $900M) in leading-edge CMOS logic and memory devices.

Integrated Materials Solutions (IMS):

• Developed EOT scaling solutions for performance enhancement in High-k Metal Gate.
• Innovated GAA high-quality IO formation and S/D contact resistance reduction.
• Collaborated closely with Tier 1 customers on path-finding activities for future technologies (BSPDN, 3D-stacked FET, 3D DRAM, 4F2 cell VCT DRAM).

EUV Patterning Technology Leadership:

• Led next-generation EUV patterning technology for exposure dose reduction (throughput improvement/cost reduction) in Logic & Memory (DRAM) applications.
• Utilized High-z based PVD or CVD UL.

Co-Optimization Solutions:

• Drove Co-Optimization solutions, including GAA (Nano-sheets) low-k inner spacer, lateral Si push, novel S/D Epi technology, Low-Temp High Quality CVD film for logic gate HM, and advanced DRAM capacitor patterning.

Customized Process Development and Materials Solutions:

• Collaborated with various Business Units to develop and transfer customized process modules and materials solutions.
• Ensured solutions met and solved customer’s high-value problems.

Customer Expertise and Strategic Partnerships:

• Served as customer expert across complex product range.
• Defined product strategy and provided feedback on process and hardware improvements.
• Formed strategic partnerships with customers to evaluate emerging technologies.

Accelerating Customer Technology Roadmap:

• Provided oversight of customer demos, defining conditions and analyzing results.
• Facilitated close interlocking with customers to accelerate technology roadmap.

Enhancing Customer Satisfaction and Reputation:

• Assisted field account teams and sales in managing tier 1 customer accounts.
• Focused on enhancing customer satisfaction and increasing product and technical reputation.

Transistor Roadmap Definition and Validation:

• Led definition of transistor roadmaps, including upcoming and future technology inflections.
• Validated product pathway solutions by leading FEOL/MOL advanced Transistor Technology Team (managed 10 engineers).

Key Contributor to $800M Generation:

• Played a crucial role in the success of >$800M generation for advanced Contact/MOL module products in leading-edge logic technology nodes.

Contact Module Process Leadership:

• Led logic device contact module processes to meet next-generation contact resistance requirements.
• Drove cross-functional product teams to validate process integration pathways, achieving over 50% contact resistance reduction and enabling new process designs.

Next-Generation 3-D Transistor Challenges:

• Identified process integration challenges and requirements for next-generation 3-D transistor architectures (e.g., FinFET, GAAFET).

Customer Engagement and Technology Sensing:

• Participated in internal technology forums, top account alignment, and customer technical meetings.
• Engaged with customers’ customers to improve product positions by addressing technology challenges and High Value Problems (HVP).

Process Technology Leadership:

• Managed and directed process technology groups responsible for research, development, and implementation across various product portfolios (ALD, CVD, PVD, Epi, Etch, CMP, IMPLAT/ Anneals/Metrology & Inspection).

Innovative Solutions and Test Vehicles:

• Developed innovative solutions and validated product development paths with cross-functional teams.
• Utilized advanced test vehicles, including FinFET and GAA (Nano-wire and Nano-sheet) transistors.

Path finding Research and University Programs:

• Led path finding research on alternative and energy-efficient switches (HZO Ferroelectric based-FETs, 2D-TMD, IGZO channel devices).
• Collaborated with universities (UC Berkeley and UC San Diego) for new materials/chemistry and device validation.

Team Collaboration and Continuous Improvement:

• Encouraged team collaboration and motivated individual employees through positive reinforcement and technical recognition.
• Successfully completed over 15 projects for key customers, driving future business opportunities.
• Facilitated continuous improvement initiatives with successful changes affecting all areas of operations.

Logic Transistor Roadmap Definition:

• Led definition of N+1/N+2 and beyond logic transistor roadmaps.
• Addressed upcoming and future technology challenges, including new channel materials (scaled Si/SiGe FinFET, Gate-All-Around).
• Identified process integration requirements and delivered superior results through internal and external benchmarks.

Technology Influence and Customer Roadmap:

• Participated in regular technology review meetings.
• Provided key technology solutions to influence customer technology roadmaps across business units (PVD/Epi/ALD/Etch/Implants/Metrology & Inspection).

Path finding and Winning Solutions:

• Led path finding activities for technology solutions (PPAC: power/performance/area/cost).
• Addressed key modules (STI/Fin, Metal Gate stack, Spacer, S/D-Epi Junction, contact/MOL) in scaled FinFET technology.
• Delivered winning solutions across various industries.

GAA Technology Development:

• Developed Gate-All-Around (GAA) technology through joint development with IMEC.
• Achieved defect-free SiGe channels, thin film band-edge WF metals, and highly-doped Epitaxial S/D junction.
• Innovated Contact processes to meet next-generation contact resistance requirements.

Advanced 3D Transistor Test Vehicles:

• Led multi-module process team to set up advanced 3D transistor (FinFET) test vehicles.
• These vehicles are utilized for evaluating new products and process integration solutions.

10nm FinFET Technology Development:

• Oversaw core, SRAM, IO, and passive device development.
  Collaborated with marketing to define competitive power/performance targets.
• Worked closely with TCAD and modeling teams to establish parametric goals.

Technical Facilitation and Process Optimization:

• Led discussions on critical process elements (fin patterning, fin profile, low-k spacer, S/D epi-junction, multi-wafer engineering).
• Contributed to design rule and process architecture definitions.

Cross-Functional Collaboration:

• Collaborated across teams (Process Integration, Unit Modules, TCAD, modeling) to meet 10nm requirements.

Device Testing Macro Development:

• Developed modeling and DOE macros for 10nm FinFET devices.
• Defined macro contents and layout using Cadence pcells.

Team Leadership and Technology Solutions:

• Managed 20nm device team of over 15 professionals.
• Led 20nm high-k/metal gate technology solutions.
• Coordinated efforts across Integration, Device, SRAM, TCAD, and modeling teams.

Focus on S/D Junction and RMG Module:

• Planned and executed device performance improvements.
• Focused on S/D junction and RMG module upgrades.
• Defined comprehensive solutions for yield and reliability.
  

Seamless Interface and Customer Collaboration:

• Facilitated communication between unit process, integration, device, and modeling teams.
• Ensured device maturity aligned with milestones and customer needs.

Customer Interlock and Validation:

• Provided process run paths for customer products. Validated spice model to hardware correlation.
• Conducted regular customer interlock meetings.

Coaching and Cross-Functional Engagement:

• Mentored engineers and staff.
• Actively participated in cross-functional discussions and led teams.
  

Team Management and Transition:

• Managed a 20nm device team of 15 professionals during the development cycle.
• Ensured a smooth transition and handoff to manufacturing teams.

Technology Development Leadership:

• Led a team driving 20nm high-k/metal gate technology development.
• Validated device performance enhancements for baseline process upgrades, achieving SRAM yield and reliability requirements.

Strategic Roadmap Execution:

• Developed an overall device improvement roadmap.
• Successfully enhanced device performance across Core, IO, SRAM, and passive devices.
• Collaborated with reliability counterparts to meet customer reliability targets.

Collaboration and Process Enhancement:

• Worked closely with the FEOL Integration Team.
• Explored options to enhance transistor characteristics through experiments.
• Established tools and infrastructure for measurement and evaluation.

Quality and Reliability Assurance:

• Participated in process change control procedures.
• Established device electrical monitors, targets, and controls.
• Ensured quality and reliability throughout the process.

20nm Metal Gate/High-k (RMG) Technology Development:

• Designed and developed CMOS logic and SRAM devices for 20nm RMG technology.
• Defined 20nm device targets and achieved performance improvements.
• Facilitated technology transfer to the home Fab (Malta Fab8, GlobalFoundries).

Core/SRAM/IO/Passive Device Development:

• Accomplished all aspects of core/SRAM/IO/Passive device development for advanced 20nm RMG CMOS technology.
• Collaborated with marketing/benchmarking teams to define technology requirements and goals.
• Specialized in device electrical targeting and process optimization.

Advanced 28LP MG/HK CMOS Logic Technology:

• Led the development of 28nm hi-k/metal gate low-power technology for early customer engagement.
• Customized device design to meet customer needs.
• Transferred technology back to the home fab (Fab1, Dresden, Germany) for volume production.

Effective Collaboration and Mentorship:

• Actively participated in discussions with multiple teams under JDA (Joint Development Agreement) to address technical issues.
• Provided guidance to junior engineers, ensuring effective problem-solving.

32/28nm High-k/Metal Gate Technology Development:

• Collaborated with ISDA 32/28nm Bulk alliance partners at IBM East-Fishkill, NY.
• Successfully executed logic device performance step-up plans and improved SRAM yield, Vmin, and leakage across cross-functional teams.

Key Role in Process/Device Optimization:

• Led device performance optimization during process upgrades (cSiGe, Spacer, Junction, gate stack engineering).
• Ensured core device performance (DC/AC) and SRAM Iread/Istby met targets.
• Completed FEOL reliability qualification, PDK delivery, and SRAM stress closure.

Metal Gate Work Function Control:

• Identified key process elements for metal gate work function control.
• Implemented innovative device designs to optimize stress and high-k dielectric performance.

Intensive Electrical Testing and Mitigation:

• Conducted intensive bench testing and characterization, addressing unique HKMG device issues.
• Mitigated variability sources from Poly/SioN tech to HK/MG tech (32/28nm) nodes.

SRAM Development and Yield Engineering:

• Actively contributed to SRAM bit cell development, electrical targeting, and characterization.
• Analyzed SRAM functionality and parametric data to improve device mismatch (Avt) and meet Vmin requirements for low leakage and high-performance SRAM cell families.

Customized 65/45nm CMOS Logic Technology:

• Successfully developed and transferred customized 65/45nm CMOS logic low-power and high-performance technologies for volume production.
• Validated novel process schemes to achieve device performance targets while minimizing standby leakage in dense SRAM cells.

Key Role in 65nm Low-Power Technology:

• Played crucial role in success of 65nm low-power technology (Alliance project with IBM/Samsung/Chartered).
• Engaged with key customers, meeting overall requirements for Logic and SRAM device characteristics. Demonstrated superior product yield to meet Iddq vs Fmax requirements.

Significant Contribution to 45nm Low-Power SRAM:

• Met Iread/Istby targets and achieved dramatic Vmin improvement through SRAM cell device optimization.
• Reduced device variability by introducing Carbon-co implantation as baseline process.

0.25um RF CMOS Development and Mass Production:

• Conducted research and development for 0.25um RF CMOS technology.
• Successfully transferred it to mass production, addressing critical device issues (INWE, double hump, Idlin degradation) through SPICE matching activities and technology solutions.

Prototyping Management and Yield Improvement:

• Successfully managed prototyping and device/process improvement for high-volume logic products, including embedded Flash/SRAM devices.
• Collaborated closely with unit process and yield engineering teams.
• Focused on device/process analysis and characterization to achieve rapid yield ramp-up.

Technology Qualification and Release for Production:

• Led technology qualification activities for logic and embedded flash memory products (0.14/0.15/0.18/0.25um technologies).
• Leveraged solid semiconductor device physics and device parametric knowledge.
• Conducted manual bench failure analysis and characterization.

Advanced CMOS Device Characterization:

• Evaluated embedded Flash/SRAM devices - electrical targeting and SPICE model matching.
• Programming/erasing window optimization.
• Mobility, charge trapping, and interface states analysis.
• Leakage assessment.
• SRAM functionality, stability, and read/write margin analysis.
• Device parameter targeting for logic and SRAM bitcell performance (Vmin).

Embedded Flash Memory Development:

• Developed 0.14um Embedded Flash Memory technologies in collaboration with Philips Semiconductor (now NXP).
• Led process improvement efforts, including photo evaluation and CMOS flash and logic device optimization.
• Ensured robust process margins for mass production.

Successful Technology Transfer:

• Transferred 0.15/0.18um CMOS logic and 0.15um Embedded Flash Memory technologies from Philips Semiconductor to SSMC.
• Qualified for release for production and managed prototyping.
• Focused on yield improvement as process owner for 0.15um flash memory devices.

DRAM Development and Manufacturing:

• Played pivotal role in research, development, and yield improvement for various DRAM generations.
• Successfully transferred mass production for Blue-Chip Projects involving 128M & 256M DDR SDRAM (0.16um technology).
• Specialized in DRAM cell engineering to meet retention time requirements through innovative memory cell junction/capacitor engineering using DOE and TCAD simulation.

Advanced Memory Cell Engineering:

• Developed 256M DRAM using 0.15um technology (Metal Gate & Ta2O5 Capacitor) to optimize memory cell transistors and improve retention time.
• Ensured compliance with in-depth device reliability characteristics (HCI & TDDB) based on the in-line process.

DRAM Cell & Periphery Device Development:

• Key integrator for 5th-64M (0.20um) & 3rd-128M SDRAM (0.18um) R&D, successfully transitioning to mass production.
• Expertise in test pattern (macros) design, TCAD simulation (OPUS, SUPREM4, MEDICI), and in-depth device electrical analysis.

DRAM Cell Retention Time Engineering:

• Addressed pause and disturbance issues in DRAM memory cells.
• Conducted device reliability evaluations (HCI & TDDB).

Electrical Analysis and Process Control:

• Managed electrical analysis during 2nd-64M SDRAM (0.20um) cell engineering and yield improvement in high-volume fabs.
• Oversaw device engineering (cell and periphery transistors), design rule generation, mask tooling, and process quality control.