Nanjundeswar Nekkondi
Milpitas,CA
Summary
- 17+ Years of experience in taping out multi-million instance designs ranging from 65nm-3nm.
- Clock Feedthru Planning, Clock Trunk Construction, Clock Duty Cycle Signoff.
- Good expertise in Constraint cleanup, Floor Planning, Congestion & Timing Placement, CTS, Routing, STA, DRC/LVS.
- Mentored junior engineers through technical guidance and hands-on training, enhancing team productivity.
- Collaborated with cross-functional teams to discuss the Physical Design Team challenges and discuss architecture changes for better closure of designs.
Overview
18
18
years of professional experience
Work History
Senior Staff Engineer
QUALCOMM INC
05.2017 - Current
Senior Staff Engineer
ARICENT NA Inc/SMARTPLAY INC
02.2013 - 04.2017
Lead ASIC Design Engineer
SMARTPLAY Pvt Ltd
05.2008 - 02.2013
Engineer
QUALCOMM IND PVT LTD
10.2007 - 04.2008
Engineer
CTS Pvt Ltd
07.2006 - 10.2007
Education
Bachelor of technology - Electronics and Communication
JNTU Anantapur
Anantapur05.2006
Skills
- Clock Planning (Feedthru and Implementation)
- Duty Cycle Signoff for Clocks (fresh and aging)
- Latest SSN DFT Scan Architecture and test clock implementation
- PnR: - ICC/ICC2, Encounter FE, Magma Talus
- Power Analysis: - Magma Blast Fusion and Redhawk
- Timing Analysis: - Primetime, Primetime SI
- Extraction: - Star RC
- Physical Verification: - ICV, Calibre LVS and DRC
- Low Power Checks: CLP
- Scripting: - TCL
Work Authorization
H1-B
Projects
TOP CTS, 01/2020 - Present, Worked on 5 projects (2 variants per project). Part of TOP CTS Team for Clock Feedthru planning. Implemented TOP Clock Tree synthesis with complex clock balancing. Was Point of Contact for TOP Test clock Implementation and Balancing. Successfully implemented new SSN DFT architecture for first time. DCD and R2R closure for Full Chip. Clock ECO analysis, Clock Balance Analysis at Top Level. TOP CLOCK POWER (5 nm), 07/2019 - 12/2019, Qualcomm native flow to get gated and ungated clock power. Flow enhancements and bug fixes in PERL and TCL for the Flow scripts. Analyze the ungated power and how to better the clock power in future chips. Propose design changes to help save power and physical location of the custom CGC. DDR CHIP (5 nm), 06/2019 - 12/2019, Floorplaning for DDRat Top with partitioning for 5 blocks/FV/CLP at Top level. MODEM WTR CHIP (14 nm), 11/2018 - 05/2019, Physical Design Chip Lead. Floorplaning for 2 blocks with partitioning at Top. Place & Route, STA, FV. Timing ECO using Tweaker at TOP Level. Monitoring a Team of 12 People in USA and India. MODEM WTR CHIP (14 nm), 05/2018 - 10/2018, Physical Design Chip Lead. Floorplaning for 6 blocks with partitioning at Top. Place & Route, STA, FV. Timing ECO using Tweaker at TOP Level. Monitoring a Team of 10 People in USA and India. MODEM WTR CHIP (14 nm), 01/2018 - 04/2018, Physical Design Chip Lead. Floorplaning for 2 blocks with partitioning at Top. Place & Route, STA, FV. Timing ECO using Tweaker at TOP Level. Monitoring a Team of 6 People in USA and India. MODEM WTR CHIP (28 nm), 11/2017 - 01/2018, Physical Design Chip Lead. Floorplaning for 2 blocks with partitioning at Top. Place & Route, STA, FV. Timing ECO using Tweaker at TOP Level. CLP at Top Level. IR Analysis at TOP Level (STATIC and DYNAMIC). Monitoring a Team of 5 People in USA and India. Majorly in India. MODEM WTR CHIP (14 nm), 05/2017 - 10/2017, Floorplaning for 4 blocks with partitioning at Top. Place & Route, STA, FV. Timing ECO using Tweaker at TOP Level. CLP at Top Level. IR Analysis at TOP Level (STATIC and DYNAMIC). DDR IP CHIP (7nm), 10/2016 - 04/2017, Floorplanning for 86 Blocks Instantiations with partitioning at Top. Place & Route, STA. Timing ECO Using PT. MODEM WTR CHIP (28 nm), 07/2016 - 09/2016, Floorplaning for 4 blocks with partitioning at Top. Place & Route, STA, FV. Timing ECO using Tweaker at TOP Level. CLP at Top Level. IR Analysis at TOP Level (STATIC and DYNAMIC). MODEM WTR CHIP (28 nm), 01/2016 - 06/2016, Floorplaning for 4 blocks with partitioning at Top. Place & Route, STA, FV. Timing ECO using Tweaker at TOP Level. CLP at Top Level. MODEM WTR CHIP (28 nm), 04/2015 - 12/2015, Floorplaning for 4 blocks with partitioning at Top. Place & Route, STA, FV. Timing ECO using Tweaker at TOP Level. CLP at Top Level. MODEM WTR CHIP (28 nm), 10/2014 - 04/2015, Floorplaning for 4 blocks with partitioning at Top. Place & Route, STA, FV. Timing ECO using Tweaker at TOP Level. CLP at Top Level. IR Analysis at TOP Level (STATIC and DYNAMIC). VIDEO CODEC CHIP (28nm), 06/2014 - 09/2014, Floorplanning for a single block. Place & Route, STA, FV and CLP. Timing ECO using tweaker at Block Level. NETWORK CHIP (22 nm), 02/2014 - 05/2014, Floorplaning of 2 Blocks. Place & Route, STA, FV, DRC & LVS. IR analysis at Block Level (STATIC and DYNAMIC). NETWORK CHIP (22 nm), 02/2013 - 01/2014, Floorplaning of 2 Blocks. Place & Route, STA, FV, DRC & LVS. IR analysis at Block Level (STATIC and DYNAMIC). Memory Test Chip (28 nm), 04/2012 - 01/2013, Floorplaning of a single block. Place & Route, STA, FV, DRC & LVS. IR analysis at Block Level (STATIC and DYNAMIC). Memory Test Chip (65 nm), 05/2011 - 03/2012, Floorplaning of a single block. Place & Route, STA, FV, DRC & LVS. IR analysis at Block Level (STATIC and DYNAMIC). Flow Development in LYNX DESIGN SYSTEM, 12/2009 - 05/2011, Library Data Preparation. Writing TCL based Checks for the Initial Version of the Flow. PnR Based ICC Flow and SYNOPSYS Tools Based FV, DRC & LVS Flow Development. For 65 to 28 Nm Technology Nodes. Block Implementation (65 nm), 05/2009 - 11/2009, Floorplaning of a single block. Place & Route, STA, FV, DRC & LVS. Timing ECO Implementation. Block Implementation (65 nm), 07/2008 - 05/2009, Floorplaning of a single block. Place & Route, STA, FV, DRC & LVS. Timing ECO Implementation. DESIGN VERIFICATION FOR MSM CHIPS, 10/2007 - 05/2008, Block Level Design Verification of AHB, TLMM and I2C. Entry Level Engineer VLSI, 07/2006 - 09/2007, Trained on VLSI Basics as a New College Grad. Worked on Tool Trainings for Mentor Calibre. Implemented a small in-house project for Netlist 2 GDSII.
Timeline
Senior Staff Engineer
QUALCOMM INC
05.2017 - Current
Senior Staff Engineer
ARICENT NA Inc/SMARTPLAY INC
02.2013 - 04.2017
Lead ASIC Design Engineer
SMARTPLAY Pvt Ltd
05.2008 - 02.2013
Engineer
QUALCOMM IND PVT LTD
10.2007 - 04.2008
Engineer
CTS Pvt Ltd
07.2006 - 10.2007
Bachelor of technology - Electronics and Communication
JNTU Anantapur
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