Navid Farazmand

Chipset Power Lead for cutting edge mobile SoCs (Google Tensor Chips)

• Led Graphics IP Power Attainment: Achieved a 3x improvement in pre-silicon measurement turnaround time and throughput in the first year; over 5x increase in workload coverage in the second year; significantly enhanced projection quality for next-generation products.
• Prevented significant power regressions through regular 3D graphics and synthetic workload regression runs, coupled with thorough analysis.
• Lead RTL-based power optimization, achieving up to 150% of the target during execution phase in the second year.
• Spearheaded a two-year data-driven workflow initiative, enhancing analytics, data visualization, debugging, and automation capabilities, putting up to the minute quality data at the fingertips of over 200 team members and partners.
• Championed detailed project planning and task tracking with modern frameworks to boost organizational efficiency.
• Cultivated a diverse engineering team focused on power attainment, Perf@Power projection, and analytics, emphasizing mentorship, professional development, and a culture of innovation and excellence.

Led product Power, Performance, and Area (PPA) attainment:

• Worked collaboratively with GPU & SoC architects, software, IP, FW, platform leads, and foundry technology operations to define optimal PPA features and configurations.
• Provided domain targets supporting overall program Perf/W targets, including software optimization, performance per clock, timing, leakage, and dynamic power considerations.
• Tracked PPA attainment throughout pre-silicon execution using architectural models, RTL simulation, and IP/SoC emulation. Advised on and approved design trade-offs and power management feature ROI analysis and tradeoff decisions to ensure project alignment with the product goals.
• Served as the official voice of PPA outlook from concept to tape-out for multiple generations of RDNA family of GPUs, the mobile graphics IP through the AMD-Samsung partnership, and post-silicon execution for Radeon Vega20 gaming and Radeon Instinct MI50/MI60.
• Acted as the interim manager for a team of expert PPA leads with an average of 15+ years of industry experience (from 2020-2021).
• Made significant contributions to the correlation and improvements of PPA projections tools and methodologies.

• Engineered pre-silicon mobile GPU kernel drivers, enhancing scheduling, state management, and memory allocation processes.
• Innovated and deployed an automated GPU power and performance profiling framework, achieving sub-100 microsecond resolution for precise analysis.
• Developed and implemented two novel Dynamic Voltage and Frequency Scaling (DVFS) solutions, significantly boosting energy efficiency and quality of service for mobile GPU workloads.

• Power management of mobile GPUs; Reliability modeling and analysis of high performance, multi-core heterogeneous architectures; Fault tolerance and reliability enhancement of emerging nanotechnologies.
• Peer-reviewed publications with ~200 citations. Reviewer for ISCA, IEEE Micro, ICCD, ACM TACO, ITC, ASAP, HPCA, JPDC.