Neeraj Dhotre
Santa Clara,CA
Summary
Proven track record of being a team player with strong problem-solving skills, contributed effectively to projects and teams, always striving to deliver high-quality robust results. Curiosity driven, always learning, questioning and applying fundamentals to solve problems.
Overview
16
16
years of professional experience
Work History
Senior Staff Engineer
Qualcomm, Modem
11.2022 - Current
- Critical Member of Fundamental architectural overhaul for Modem Hardware by implementing Virtual Memory Management in hardware to save ~10% area.
- Cross functional teams (Software, Firmware, DV, Design) buy in to finalize spec.
- Micro architecture and RTL implementation from scratch.
- Smooth execution and design ready to be used multi generations of Modem ASIC with future add on features in FW/Software.
Staff RTL Design Engineer
Qualcomm, 5G Oran
03.2020 - 11.2022
- Designer for Compute Intensive block Down Link MIMO Beam Forming. Support 32 antenna ports 24 layers with 768 complex multipliers and 384 dual port memories, 5nm node.
- Micro architecture and cross functional spec finalization. All Design and RTL from scratch of version 1.
- Designer for custom DMA and Axis interfaces to pump compute data out.
- Lead 8 member team execution in version 2, solved PD congestion issues and optimized area and power.
Staff RTL Design Engineer
5G Modem Uplink
03.2018 - 03.2020
- Design owner of multiple blocks over 3 generations of 5G Modems
- WOLA, FFT operation, Vector Processor, Filtering
- Responsibilities included being part of 5G spec discussions as a representative of HW impact, micro architect memory usage, timeline and performance, collaborate with remote teams to implement RTL, develop verification plan and perform RTL quality checks, integration, synthesis and power flows
- Top performer in fast paced and dynamic team environment
- Experience with multiple chips, silicon debug and ECOs.
Power Estimation/Optimization
Digital Modem Power
03.2016 - 03.2020
- Team member creating unified power model for Digital Modem. Always helping with power along with designer responsibilities.
- Daily work includes PTPX runs, Leakage analysis, scenario based power analysis and peak power analysis
- Developed flows, scripts to use and run these tools effectively for our needs
- RTL power optimization with PowerPro and effective hard macro, memory power collapse.
Engineer
Qualcomm, LTE Search, Demapper Firmware
03.2013 - 04.2015
- Assembly coding at the boundary of firmware and hardware
- Involves craftsmanship to build power efficient Modem by doing Memory Maps, Vector Processing assembly code, timeline design and Cycle Count optimization
- Implemented assembly code for in house vector processor (DSP)
- Designed flows, tutorials and mentored other engineers to ramp up on in-house methodologies and architecture.
Design Verification (UVM)
04.2015 - 03.2015
- Familiar with UVM flows, constrained random testing, functional and code coverage
- Have contributed to DV team stints after design completion to help meet deadlines.
Design Implementation Engineer
PMC-Sierra (now Microsemi)
01.2009 - 01.2011
- Worked as Design implementation engineer for RTL synthesis, DFT scan stitching, Static Timing Analysis
- Acquired skills to run CAD tool flows and scripting with PERL and Python
- Main Tools used include Goldtime, Cadence RTL compiler, Cadence Encounter Test.
Education
MS - VLSI and Computer Architecture
University of California, Santa Barbara
Santa Barbara, CA01.2013
B.E. (Honors) - Electrical and Electronics, MSc. Physics
Birla Institute of Science and Technology
Goa, India01.2009
Skills
- ASIC Design and Micro Architecture
- Digital Design, System Verilog, RTL Design
- Cycle and Power Characterization, PTPX
- Digital Implementation, Link check, Synthesis
- Strong fundamentals in Comp Arch, algorithms and data structures, enabling Scripting and flow setup
- 7 years of experience on LTE and 5G physical layer protocol implementation
- Tech leadership, proactive working style and getting things done
Timeline
Senior Staff Engineer
Qualcomm, Modem
11.2022 - Current
Staff RTL Design Engineer
Qualcomm, 5G Oran
03.2020 - 11.2022
Staff RTL Design Engineer
5G Modem Uplink
03.2018 - 03.2020
Power Estimation/Optimization
Digital Modem Power
03.2016 - 03.2020
Design Verification (UVM)
04.2015 - 03.2015
Engineer
Qualcomm, LTE Search, Demapper Firmware
03.2013 - 04.2015
Design Implementation Engineer
PMC-Sierra (now Microsemi)
01.2009 - 01.2011
MS - VLSI and Computer Architecture
University of California, Santa Barbara
B.E. (Honors) - Electrical and Electronics, MSc. Physics
Birla Institute of Science and Technology
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