Summary
Overview
Work History
Education
Skills
Projects
Timeline
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Nibir Islam

South Burlington,VT

Summary

Experienced Electrical Engineer with 5 years of experience in digital circuit designing in volatile & non-volatile memory. Skilled in digital design, verilog testbenches, behavioral models & debugging.

Overview

6
6
years of professional experience

Work History

Circuit Design Engineer

Green Mountain Semiconductor
05.2018 - Current
  • Currently working on 8nm OTP performing signal integrity analysis & extended PVT analysis
  • Worked on the design & signal integrity analysis of a 3nm ROM project
  • Worked on 5nm ROM project performing timing analysis & signal integrity analysis
  • Worked on eDRAM design with 14nm fin technology. Created verilog behavioral models, testbenches & vectors for verification purpose
  • Worked on Chip Level simulations & timing analysis
  • Worked on Block level designing & layout using Cadence tools
  • Worked on designing & implementing block using RTL coding techniques
  • Previously worked on a PCM (Phase Change Memory) chip.

Circuit Design Intern

Green Mountain Semiconductor
12.2017 - 05.2018
  • Worked on designing Schematics and Layouts Memory Circuits on Cadence Virtuoso
  • Obtaining good working knowledge about CMOS Technology.

Graduate Teaching Assistant

University of Vermont
  • Worked as a teaching assistant for Linear Circuit Design and Embedded Systems course
  • Supervised students in Designing RLC circuits and simulating electrical circuits on LTspice.

Education

MS in Electrical Engineering -

UNIVERSITY OF VERMONT
Burlington, VT
05.2018

Bachelor of Science in Electrical & Electronics Engineering -

AMERICAN INTERNATIONAL UNIVERSITY OF BANGLADESH
Dhaka, BD
05.2016

Skills

  • Matlab
  • Verilog
  • shell scripting
  • Cadence Virtuoso
  • Nanotime
  • Spice & spectre simulation tools
  • Circuit checking tools (DRC, LVS)
  • RTL
  • Python Scripting
  • ASIC design & verification
  • Gate-level logic design

Projects

i) Power Flow Project, University of Vermont, Burlington, VT, Fall 2017

Developed a progressively advanced understanding of the N-R method and how it applies to solving different power flow problems, MATLAB Finding Power Law Distribution in Cascade Failures, University of Vermont, Burlington, VT, Fall 2017, Investigated the presence or absence of power law distributions in cascade simulations for 2383 bus Polish grid system Integration of Smart Hybrid

ii) Uninterruptable Power Supply using Hydro and Solar, Fall 2015

Used solar panels and a micro hydro generators with the connection of DPDT relay to design and implement Hybrid UPS, Proteus software, Matlab CAD Designer

Timeline

Circuit Design Engineer

Green Mountain Semiconductor
05.2018 - Current

Circuit Design Intern

Green Mountain Semiconductor
12.2017 - 05.2018

Graduate Teaching Assistant

University of Vermont

MS in Electrical Engineering -

UNIVERSITY OF VERMONT

Bachelor of Science in Electrical & Electronics Engineering -

AMERICAN INTERNATIONAL UNIVERSITY OF BANGLADESH

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Nibir Islam