Nidhi Gupta
Charlotte
Summary
- 15+ years of experience in system design across US and Indian companies, with a strong track record of delivering high-performance digital and embedded solutions for telecommunications, medical, industrial automation, scientific research, and measurement applications.
- Agile & Distributed Collaboration: Proven ability to lead R&D initiatives, apply Agile/Scrum best practices as CSM and CSPO, resolve complex technical challenges, and act as a bridge between engineering and product teams to ensure timely completion.
- Hardware/Firmware Development: Proficient in schematic capture, PCB layout, and implementation of advanced digital systems using both on-board and on-chip components. Expertise spanning circuit design, complex RTL, and embedded firmware (SoC/MCU/FPGA). Strong background in integrating FPGAs with memory, data converters, and microcontrollers (MCUs).
- FPGA/SoC Tools & Methodologies: Deep hands-on experience with Intel (Quartus, ModelSim, Platform Designer) and Xilinx toolchains (Vivado 2020.2+, Vitis 2025.1). Skilled in RTL design, timing closure (STA, CDC), high-level synthesis (HLS), SoC development with embedded processors, and verification with SystemVerilog/UVM, Advanced AI/FPGA Acceleration
- Hardware/Software Integration & Protocols: Expertise in communication protocols including JESD204B/C, PCIe, USB, UART, SPI, and I2C. Experienced in building GUI applications with C#/C++ for scientific instrumentation, and hardware evaluation platforms.
- Scripting & Automation: Developed Python, Shell, Make, and TCL scripts for hardware validation, testbench automation, and continuous integration of FPGA builds.
Overview
19
19
years of professional experience
Work History
ELECTRONICS DESIGN ENGINEER
GE
04.2024 - 10.2024
- Contributed to project planning and execution in roles as Scrum Master, Product Owner, and developer, ensuring timely delivery and alignment with Agile principles.
- Collaborated with the Product Owner/Manager to prioritize the backlog, deriving clarity and focus through an understanding of team workflows.
- Contributed majorly to obsolescence and change management for legacy electronic designs, extending product life and enhancing system functionality.
- Executed hardware development tasks, including circuit analysis, simulation, and layout modifications, contributing to robust design validation.
- Ensured functional correctness of prototype hardware after critical component replacement using GE's proprietary platforms.
- Facilitated cross-functional communication across globally distributed teams through structured weekly meetings, enhancing collaboration and issue resolution.
- Promoted Agile best practices, offering ongoing support and clarification on Scrum principles.
FPGA/FIRMWARE ENGINEER
DANFOSS LLC
10.2023 - 11.2023
- Virtualized Xilinx FPGA toolchains in VMware Workstation, enabling OS-independent, portable development environments and reducing developer onboarding time by ~30%.
- Finalized module interface requirements through detailed stakeholder interactions, ensuring smooth integration and minimizing design conflicts.
- Analyzed Spartan-6 RTL and critical module test benches to improve verification coverage, and ensure robust FPGA design.
STAFF ENGINEER
ANALOG DEVICES
05.2021 - 06.2023
- Owned end-to-end FPGA development of the Protocol Analyzer and Generator (PAG) platform on Xilinx Virtex Ultrascale+, enabling evaluation of high-speed RF data converters (JESD204x-compliant Apollo/MxFE series).
- Developed AXI-based SoC architectures integrating HBM controller, JESD204 PHY, and custom peripheral interfaces, achieving high-throughput data flow via DMA controllers using Verilog/SystemVerilog.
- Designed, developed and verified top-level testbenches using Xilinx Vivado and Cadence Xcelium, simulating complex IP blocks and identifying performance bottlenecks in loopback testing environments.
- Implemented Python scripts to control FPGA boards (ADS9/10) and data converters (TxFE/MxFE) via registers, enabling automated data acquisition and testing.
- Collaborated cross-functionally with design, test, and applications teams across geographies; maintained detailed technical documentation and updates through Confluence to support knowledge sharing and alignment.
SOFTWARE ENGINEER IV
Sterling Medical Devices
09.2020 - 03.2021
- Customized VHDL sub-modules for imaging pipelines, optimized DDR4 streaming interfaces, and developed self-checking testbenches, ensuring functional correctness and timing closure in FPGA-based systems.
SR. FPGA FIRMWARE ENGINEER
ASML
01.2020 - 08.2020
- Documented functional/electrical requirements, participated in design reviews, and analyzed FPGA architectures including BiSS interface integration, reducing design iteration cycles by 20%.
Scientific Officer
DAE, India
Mumbai
09.2005 - 01.2020
- Led FPGA-based system development for scientific instrumentation, architected modular DAQ solutions, and implemented real-time algorithms for high-throughput data acquisition, accelerating experimental workflows by 10×.
- Supervised procurement, vendor coordination, and cross-functional collaboration while managing geographically distributed teams, cutting project delays by 25% through streamlined hardware/software co-design and GUI integration.
- Mentored engineers and interns, fostered agile practices, and delivered reliable, modular FPGA solutions, boosting team productivity and efficiency.
- (INDIA)
Education
M. Tech. - Electrical Engineering
Indian Institute of Technology (IITK)
Kanpur, IndiaB. Tech. - Electronics & Communication Engineering
Kurukshetra University
IndiaSkills
- FPGA development
- Circuit design
- Hardware validation
- System integration
- Testbench development
- Agile methodologies
- Verilog/SystemVerilog
- ASIC
- Vendor coordination
- Project management
- Effective communication
- Scrum practices
- Problem solving
- Cross-functional collaboration
- Product lifecycle management
- Microcontroller programming
- Component selection
- PCB
- SoC
- Embedded (MCU/MPU)
- OrCAD
- Protel/Altium
- LTspice
- C/C
- Spice
- MATLAB
- Xilinx ISE/Vivado/Vitis
- Modelsim/Questasim
- Altera Quartus
- VHDL
- Verilog
- SystemVerilog
- Python
- TCL
- Make
- Shell
- JESD204B/C
- PCIe
- USB
- Ethernet
- JTAG
- SPI
- I2C
- LVDS
- VME
- HART
- RS232
- 8051 MCUs
- ARM
- AXI
- Microblaze
- Keil µVision
- Eclipse
- Labwindows/LabVIEW
- Visual Studio
- Visual Basic
- C#
- Oscilloscopes
- Logic analyzers
- DVMs
- Signal generators
- Spectrum Analyzers
- JTAG debug tools
- Coaching
- Facilitation
- Leadership
- Continuous Improvement
- Estimation
- Analysis
- Cross-functional Collaboration
- Product Lifecycle Management
- JIRA
- Confluence
- SVN
- Git
Websites
Projects
- DEVELOPMENT OF JESD204 ANALYZER, FPGA-based design for IC verification and characterization of high-speed RF data converters (ADCs and DACs)., Worked on RTL design and Python/TCL scripting for a complex AXI bus-based SoC targeting a Xilinx Virtex Ultrascale+ FPGA with HBM controller and JESD204 PHY.
- IMAGE SIGNAL PROCESSING PIPELINE FOR BLOOD SAMPLE ANALYZER, SoC design (Intel Arria10) for a high-speed image signal processing (ISP) pipeline to detect patterns in blood samples., Contributed to VHDL coding, testbench creation, simulation, and on-board debugging.
- ADVANCED SCIENTIFIC INSTRUMENTS, Proposing and demonstrating a modular hardware design approach using a System-On-Module (GPM) with an Spartan6 FPGA and microcontroller., Designed and developed a custom SOM with USB interface to meet multiple application needs and proposed later versions with Ethernet, and PCI interfaces.
- PC-BASED MULTI-CHANNEL SCALARS, Developing variants of an instrument that records the counting rate of events as a function of time., Responsible for the entire development process, including circuit design, layout, FPGA logic design, and documentation.
- TIME CORRELATION ANALYSIS, Scientific instrumentation and algorithms for analyzing time-correlated pulse data in reactor applications., Developed algorithms for real-time fuel monitoring and implemented them in hardware.
- PULSE ARRIVAL TIME RECORDER, Design of an advanced instrument (NuSITAR) for recording pulse arrival times with 5nsec resolution., Managed the full development cycle, including requirements, FPGA logic design, coding, simulation, and testing.
- CUSTOM BISS MASTER INTERFACE, Firmware development for a motion control system in a complex lithography machine., Developed and integrated a custom BiSS-C Master interface, improvising existing VHDL design and testbench code.
- RATIO TO DIGITAL CONVERTER, Indigenous development of legacy instruments by integrating FPGA and microcontroller into the design., Responsible for design analysis, modifications, and the development of conversion algorithms.
- LOW NOISE ASIC FOR X-RAY DETECTORS, Design and development of a low-noise analog pulse-processing ASIC in 0.7µm CMOS technology for Silicon Drift Detectors., Performed design analysis, simulation, layout, and prepared for final tape-out.
- VME BUS EMULATOR, Development of a microcontroller-based VME bus card for in-house testing and diagnostics., Responsible for Circuit Design, MCU firmware coding, debugging, and in-system testing.
- VME BUS INTERFACE CONTROLLER, FPGA-based custom design to replace a commercial ASIC for VME bus interface control., Managed the entire design process, including micro-architecture development, VHDL coding, simulation, and validation.
Technical Pursuits
- FPGA-based DSP/AI Acceleration (Xilinx Vitis, Versal AI Engines)
- High-speed IO/Protocols (JESD204B/C 12.5Gbps, PCIe Gen4 16GT/s, 10/25GbE)
- SerDes for Gigabit Transceivers & Signal Integrity Analysis
Education Certifications
- Certified Product Owner, Scrum Alliance
- Certified Scrum Master, Scrum Alliance
- 6-month program on Artificial Intelligence, and Machine Learning, NIELIT & IIT Ropar, India, 7.9
- 3-month course on IO Concepts and Protocols (PCI Express and Ethernet), UCSC
- 3-month course on Comprehensive Signal & Power Integrity for High-Speed Digital Systems, UCSC
- M. Tech. (Electrical Engineering), Indian Institute of Technology (IITK) Kanpur, India, 4.0
- B. Tech. (Electronics & Communication Engineering), Kurukshetra University, India, 3.78
Timeline
ELECTRONICS DESIGN ENGINEER
GE
04.2024 - 10.2024
FPGA/FIRMWARE ENGINEER
DANFOSS LLC
10.2023 - 11.2023
STAFF ENGINEER
ANALOG DEVICES
05.2021 - 06.2023
SOFTWARE ENGINEER IV
Sterling Medical Devices
09.2020 - 03.2021
SR. FPGA FIRMWARE ENGINEER
ASML
01.2020 - 08.2020
Scientific Officer
DAE, India
09.2005 - 01.2020
M. Tech. - Electrical Engineering
Indian Institute of Technology (IITK)
B. Tech. - Electronics & Communication Engineering
Kurukshetra University