Nisha Joshi
Chandler
Summary
Dynamic Analog Design Methodology Manager at Intel with 14 years of experience in RTL to GDS and analog IC design. Proven leader in quality assurance, achieving an 85% reduction in customer issue rates. Skilled in PDK methodologies and adept at driving cross-geo collaboration for best-in-class product execution.
Overview
15
15
years of professional experience
1
1
Certification
Work History
Analog Design Methodology Manager
Intel
Chandler
04.2020 - Current
- Part of Validation organization for the Foundry Process Design Kit team, I was responsible for creating a team and putting process in place for driving release of quality analog libraries of PDKs
- Drove deliverables with limited Resources without impacting quality.
- Reduced the issue rate found by customers by 85% for analog Libraries.
- Created validation process, KPIs and strong Quality Plan methodology to minimize escapes.
- Successfully trained cross -geo teams on the Quality methodology put in place.
- Introduced multiple projects including virtuoso router capability to reduce the manual effort to create analog testcases for testing
- Built timer, clamps & PLL testcases to add comprehensive coverage.
Component Design Engineer (Fullchip Design)
Intel
Chandler
06.2018 - 04.2020
- Full chip and hierarchical collateral development for 10nm, 7nm Process design kits.
- Supporting Tape-in teams with unique issues to help them clean their DRC at full chip Level.
- Successfully build DIC wrappers, shims and enabling it in QA suite.
- Also building testcases like mini die to tests collaterals like DIC, shims, Etch Ring, Edge damage monitor rings for each process and adding them to QA suite.
- Helped in the automation of QA results be sent in an email to the team for fast debug and access to resolve issues in time for release.
Interim Technical Program Manager
Intel
Chandler
02.2018 - 07.2018
- Process improvement task including tickets driven display to planners to establish the content going in the release. This has helped the Planning Reps to scope out specs and freeze the spec with less ambiguity.
- Driving 14nm and 10nm process collateral creation to release Process Design kits to internal design teams. This includes working and driving people to provide collaterals from R&D, providing it to PDK teams to build/QA and then release.
- Creating a system with stakeholder input to have a request form to streamline the process/dot process requests instead of via emails
Component Design Engineer (ASIC)
Intel
Chandler
12.2011 - 05.2018
- Block Level implementation synthesis to timing closure for various technologies - 14nm, 10nm using Synopsys tools Design compiler, ICC2, Primetime
- Driving work groups with sub teams to drive the solution of issues found during QA like drc fixing, timing analysis
- Process improvements tasks including synchronizing of QA run results across sites Bangalore and Chandler sites via web to be visible to stakeholders
- Driving efficiency efforts within groups to make release process smooth by working with engineers with automate graph generation and report generation via Database so that stakeholders can independently access data.
Research Intern
Indian Institute Of Technology, Bombay
Bombay
05.2010 - 07.2010
- Designed and analyzed a 1024 X 8 memory module for the ASIC System
- Assembled row decoder, 6T SRAM cell, sense amplifier and read/write circuit
- Communicated with Cadence support team to solve the compatibility issues of .oa files in NCSU library
Education
Master of Science - Electrical & Computer Science
University of Illinois at Chicago
Chicago05.2011
Bachelor of Engineering - Electrical & Computer Engineering
Visveswaraya University
India07.2009
Skills
- Strong leader/manager who can be involved in both business and technical decisions
- Analog design methodologies for PDKs
- Quality assurance for PDKs
- MSEE, plus 14 years of RTL2 GDS, lint checks, full-chip collateral, and analog IC design, and clamp design
- Dynamic individual who drives with a learning mentality, with best-in-class product execution
- Programming languages: Tcl, Cshell, Perl, Python (learning)
- System design tools: Virtuoso, Custom Compiler, Calibre, Design Compiler, ICC, ICC2, ICV, Primetime
- Office: Word, Excel, PowerPoint, Project
Certification
- PMP Certfied
Accomplishments
- Paper Published at Intel Journal : " Multifaceted generic approach to the validation of pcell and pycell in PDK libraries and associated challenges"
Timeline
Analog Design Methodology Manager
Intel
04.2020 - Current
Component Design Engineer (Fullchip Design)
Intel
06.2018 - 04.2020
Interim Technical Program Manager
Intel
02.2018 - 07.2018
Component Design Engineer (ASIC)
Intel
12.2011 - 05.2018
Research Intern
Indian Institute Of Technology, Bombay
05.2010 - 07.2010
Master of Science - Electrical & Computer Science
University of Illinois at Chicago
Bachelor of Engineering - Electrical & Computer Engineering
Visveswaraya University
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