PADMA KUMAR PEDIREDLA
Austin,TX
Summary
Creative and innovative prospect determined to bring ideas to life through cutting-edge technology and design techniques. Team player with strong problem-solving skills to contribute effectively to projects and teams. Considers unique and unconventional solutions to deliver exceptional results.
Overview
17
17
years of professional experience
Work History
Senior Consulting Physical Design Engineer
Meta
10.2021 - Current
- Working on 4nm/5nm , multiple complex blocks with challenges achieving best QOR for timing , power , IR analysis
Senior Consulting Physical Design Engineer
Apple
03.2021 - 10.2021
- Worked on 5nm technologies and high speed design
Lead Engineer
Intel
09.2018 - 03.2021
- Worked on 10nm project with a frequency of 1.2 GHZ
Senior Technical Lead Physical Design Engineer
Aricent NA Inc
08.2016 - 03.2021
- Worked on 10nm project with a frequency of 1.2 GHZ
Lead Engineer
AMD
08.2016 - 08.2018
- Worked on 7nm TSMC GPU project on block level with a frequency of 2GHZ
Technical Lead Physical Design Engineer
Aricent
12.2012 - 07.2016
- Worked as a Technical Lead Physical Design Engineer for Aricent, Bangalore, India from Dec 2012 to Jul 2016
Senior Physical Design Engineer
AMD
01.2011 - 11.2012
- Worked as a Senior Physical Design Engineer for AMD, Hyderabad from Jan 2011 to Nov 2012
Physical Design Engineer
ARM Technologies Pvt Ltd
01.2007 - 12.2010
- Worked as a Physical Design Engineer for ARM Technologies Pvt Ltd, Bangalore from Jan 2007 to Dec 2010
Education
Master of Science - VLSI
Manipal University
Manipal03.2005
Skills
- Overall experience of 15 years in VLSI Physical Design
- Very good experience in P&R, STA, EMIR, Custom place and route of IP, synthesis, ECO flows and Physical Verification
- Expertise in physical design implementation includes Floor planning, power planning, Placement, Clock Tree Synthesis (CTS), Routing, Extraction, ECO, Timing closure, IR drop Analysis and Physical verification
- Expertise in resolving various Block level issues including Timing, congestion, EM/IR, Crosstalk
- Expertise on low power design implementation and power analysis
- Hands on experience in handling different EDA tools - ICC/ICC2, Fusion compiler, PrimeTime, Design Compiler, Caliber, Star RC-XT, PTPX, Red-hawk
- Resolve Design and flow issues related to physical design, proactively identify potential issues and drive execution to ensure design PPA target convergence
- Working in collaboration with cross-functional teams like logic design/cad teams, analyzing design, flow issues and solving them early in the flow
- Good experience in scripting languages TCL
- Expertise in guiding the teams in resolving various place and route issues, including checklists, flow issues and place and route issues at different stages of design
- Ability to work independently as well as part of a team
- Very Good experience in interacting with the teams in different locations
- Placement Optimization
- Clock Tree Synthesis
- Digital Circuit Design
- IR Drop Analysis
- Routing Techniques
- Advanced Node Technologies
- Cross-talk Reduction
- Scripting and Automation
- Extraction and Back-annotation
- EDA Tool Proficiency
- Timing Closure Techniques
- Electromigration Analysis
- Synthesis and Place
- Parasitic Extraction
- Low Power Design
- Static Timing Analysis
- Signal Integrity Analysis
- Physical Verification
- Floorplanning Expertise
Experience Profile
- Meta (Facebook), 10/01/21, present, Senior Consulting Physical Design Engineer
- Apple, 03/01/21, 10/01/21, Senior Consulting Physical Design Engineer
- Aricent NA Inc, 08/01/16, 03/01/21, Senior Technical Lead Physical Design Engineer
- Intel, 09/01/18, 03/01/21, Lead Engineer
- AMD, 08/01/16, 08/01/18, Lead Engineer
- Aricent, Bangalore, 12/01/12, 07/01/16, Technical Lead Physical Design Engineer
- AMD, Hyderabad, 01/01/11, 11/01/12, Senior Physical Design Engineer
- ARM Technologies Pvt Ltd, Bangalore, 01/01/07, 12/01/10, Physical Design Engineer
Timeline
Senior Consulting Physical Design Engineer
Meta
10.2021 - Current
Senior Consulting Physical Design Engineer
Apple
03.2021 - 10.2021
Lead Engineer
Intel
09.2018 - 03.2021
Senior Technical Lead Physical Design Engineer
Aricent NA Inc
08.2016 - 03.2021
Lead Engineer
AMD
08.2016 - 08.2018
Technical Lead Physical Design Engineer
Aricent
12.2012 - 07.2016
Senior Physical Design Engineer
AMD
01.2011 - 11.2012
Physical Design Engineer
ARM Technologies Pvt Ltd
01.2007 - 12.2010
Master of Science - VLSI
Manipal University
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