Parth Patel
San Jose,CA
Summary
Senior Verification Engineer specializing in functional verification and UVM methodology. Developed test strategies and achieved coverage closure while driving project success through effective collaboration with cross-functional teams. Experienced in regression testing and skilled in SystemVerilog.
Overview
2027
2027
years of professional experience
Work History
Senior Verification Engineer
PsiQuantum Inc
Palo Alto, California
2025 - Current
- Drove growth of startup building first useful quantum computer through key contributions.
- Owned verification of fusion network aggressor block for photon control modules essential for QUBIT generation.
- Developed and maintained verification plans, test strategies, and test cases for functional block designs to ensure quality and reliability.
- Fusibility checking based on space/weight/time, candidate vs select photon,time sync algorithm are few cutting feature verified.
Senior Verification Engineer
CISCO Systems
2022 - 2024
- Full chip-verification for 51.2TB routing chips with integrated ethernet
- Verified priority-based flow control, pause, and skid features for company's first 51.2TB routing ASIC, ensuring comprehensive full chip functionality.
- Unicast/Multi cast, Oversubscribe & Congestion creation are other features own at full chip verification. Added new test cases/Modified existing ones to make it compatible at different levels of simulation at the chip.
- Injected CRC errors at main die/chiplets, confirming detection and correct generation of retransmit frames while tallying retransmit counters to prevent dropped or timed-out packets.
- Maintained regression triage for multiple chip regressions and updated results on the dashboard weekly.
- Reproduced bugs from previous tape-out, generated vectors for power analysis, and executed performance analysis regression to enhance reliability.
Staff Verification Engineer
INPHI Corporation
2019 - 2021
- Developed UVM-based environment for verification of company's first generation hybrid PLLs, ensuring robust testing framework.
- Designed and executed regressive test cases for FSM verification in PLL digital block, validating performance across multiple supported data rates.
- Led verification of previous generation MCU subsystem, adapting testbench and test cases to meet evolving project requirements.
- Verified hybrid PLL and MCU subsystems
Senior Verification Engineer
INPHI Corporation
2017 - 2018
- Verified INPHI's TIA/driver chips from verification plan to coverage closure, ensuring compliance with design specifications.
- Conducted TIA/driver chip verification for digital blocks, ensuring all specifications were met.
- Modified existing UVM-based testbench/testcases for enhanced reusability and efficiency in future projects.
- Added extra tests for coverage closure by writing Verilog behavioral models.
- Extensively working on industry standard protocols like SPI/I2C protocols. Implemented RegisterAbstraction-Layer (RAL) model to use UVM built in sequences for verification.
- Collaborated with analog team to clarify requirements, expediting development process and supporting timely market release.
Verification Engineer
Xilinx
2012 - 2016
- Developed self-checking UVM based re-usable test bench with building components like Monitor, Driver, etc.
- Added constraints, wrote assertions/assumptions properties to verify blocks like CLB, Interconnect, BRAM and RCLK throughout Xilinx's 20nm & 16nm product tap-outs.
- Added test cases/assertions and debugged legacy tests and test environment to ensure comprehensive verification.
- Functional verification of FPGA's highly configurable logic block (CLB).
- Created coverage unreachability flow using IEV to identify unreachable code, streamlining test case development.
- Created PERL scripts to exclude all uncovered signals using IMC to achieve 100% code coverage used by different team throughout production tap out.
- Deployed formal apps like X-checks, Bus-checks, X-Propagation checks on design blocks. Created formal verification infrastructure for full chip design using IFV (Incisive Formal Verifier) & Jasper.
- Collaborated with jasper/Cadence AE to improve formal verification flow, increasing efficiency of verification processes at Xilinx.
Education
M.S. - Electrical Engineering
San Jose State University
01-2012
B.E. - Electronics & Communication
Gujarat University
01-2009
Skills
- Functional verification
- Verification planning
- Regression testing/ Test case development
- Coverage-driven verification
- UVM methodology
- SystemVerilog / Verilog
- VCS/IRun/Questa/ Verdi/ simvision
- Incisive Formal verifier
- Ethernet
- I2C / SPI / APB/ AHB
- Perl
- Shell / Makefile
- SVN / Perforce/ Git / GitLab
- Vscode
- Familiar with Cursor/ Codex/ Claude
Projects
- 10GB-Mac Ethernet Verification using UVM, University of California at Santa Cruz ext.
- Hardware Implementation of logarithm function with up to 14 bits, San Jose State University
- Verification of SOC Communication using AMBA bus specifications accuracy, San Jose State University
Training
- UVM Training - UCSC
- System Verilog Training - UCSC
- Formal Verification - Xilinx
- Leadership Workshop - Xilinx
Experience Highlights
- Defined verification environment & test plan
- Developed testbench components to meet specification requirements
- Integrated testbench components at block and system level
- Developed configurable scoreboard to compare packets
- Debugged SoC level bugs in optical PHY
- Debugged block level regressions
- Delivered reusable verification environments
- 6 (1 SoC + 5 ASIC) major tape outs / functional verification signoff
- Hands on expertise in implementation & debugging Verification env.
- Detailed understanding of computing system architecture
- 6 Years of strong experience at industry leading product companies
- Experience in mentoring new batch of graduates
Timeline
Senior Verification Engineer
PsiQuantum Inc
2025 - Current
Senior Verification Engineer
CISCO Systems
2022 - 2024
Staff Verification Engineer
INPHI Corporation
2019 - 2021
Senior Verification Engineer
INPHI Corporation
2017 - 2018
Verification Engineer
Xilinx
2012 - 2016
M.S. - Electrical Engineering
San Jose State University
B.E. - Electronics & Communication
Gujarat University