Parth Shah

• Managed and technically led a team of 5 RTL engineers in the successful design and implementation of a high-performance, low power Integrated System Clocking IP (ISCLK) for Intel Client Products
• Led the development of Micro-architecture for a Soft-IP that seamlessly integrates Hard-IPs from External (TSMC, Samsung) and Internal process nodes (Intel Foundry).
• Managed end-to-end IP execution including planning, tracking and delivery of RTL from Concept to tape-out.
• Collaborated with multiple cross function teams

Architecture team to understand the feature requirements at a product level and built micro architectural specifications

Pre-SI Simulation/Emulation verification teams in development, debug and signoff

Physical design team on floor planning, timing convergence signoff

DFT team to improve Stuck@ and @Speed coverage

Circuit designers to review the HIP architecture and ensuring handshake compliance for optimal IP performance

• Collaborated with post-SI teams on testplan development, silicon bring up and drove debug activities in sort, class, HVM, system validation and bench DV.

• 1+ year of experience debugging and validating power management and Audio subsystem solutions for Intel PCH
• 6+ months of experience debugging and validating USB2/3 DBC tool for customer closed chassis debug (DFX).

• Worked on PHY layer logic design for PCIe/DMI Gen 3.0 and Display I/O
• Proficient in writing UPF (Unified Power Format) for entire analog and digital blocks, In-depth knowledge of power architecture for PHY, Conducted NLP simulations and updated UPF for multiple projects, UPF writing involved PSTs, isolation, level shifter, power gates, power muxes, and retention strategies
• Owned running, analyzing and fixing issues for FE quality checks such as lint, CDC and spyglass VCLP
• Represented RTL team for IP integration into SOC and debug functional issues to facilitate integration.