Pranav Athigaman
Austin,TX
Summary
ASIC Engineer with 5+ years of experience in DFT and design verification. Proven track record of contributing to successful tapeouts and silicon bringups across multiple SoCs. Adept at debugging, generating test patterns, developing verification environments, and cross-functional collaboration.
Overview
7
7
years of professional experience
Work History
HSIO DFT Design Verification Engineer
AMD
07.2025 - Current
- Performed design verification activities for PCIe HSIO DFx features.
- Developed, maintained, and improved test libraries for IP-level testing.
- Provided technical support to SoC and Post-Si teams to ensure successful bring-up.
DFT–DV Engineer
Apple Inc.
08.2019 - 07.2025
- Created and executed comprehensive verification plans for Apple SoC designs.
- Collaborated with designers to ensure robust DFT architecture functionality.
- Verified features of DFT architectures, analog IPs, and custom memories.
- Developed ATE test patterns and supported silicon bringup.
- Root-caused RTL bugs, built testbenches, debugged XPROP/UPF sims, ensured DV coverage.
Digital Design Engineer
Texas Instruments
02.2019 - 07.2019
- Performed verification/DFT tasks for mixed-signal SerDes chipsets.
- Integrated Cadence VIP for CSI-2 protocol validation over C-PHY.
- Generated/debugged ATPG scan chain patterns using Modus.
Education
Bachelor of Science - Electrical Engineering
The University of Texas At Austin
Austin, TX12.2018
Skills
- Verilog, SystemVerilog, Python, Perl, TCL, Linux, Cadence/Synopsys Tools, Post-Silicon ATE Debug, Confluence/JIRA
Timeline
HSIO DFT Design Verification Engineer
AMD
07.2025 - Current
DFT–DV Engineer
Apple Inc.
08.2019 - 07.2025
Digital Design Engineer
Texas Instruments
02.2019 - 07.2019
Bachelor of Science - Electrical Engineering
The University of Texas At Austin