Pranav Chava

• Developing, Debugging & Integrating new tests for Digital interfaces & Integrated Chipsets. Automating the test racks using TCL & PY scripting
• Pre-Silicon validation through FPGA emulation with tools such as Palladium and Protium
• Work closely with hardware design engineers to debug silicon issues exposed during testing. Support product development builds locally and remotely

Leadership

• Lead firmware design & performance optimization efforts for 3 generations (3 years) of 3D-NAND Flash memory. Achieved media (NAND) performance leadership for QLC (4-bits per cell) and SLC (1-bit per cell) technologies
• Lead interdisciplinary post-Silicon debug task forces to root-cause critical issues blocking product qualification
• Mentored entry-level engineers. Delegated tasks to junior team members, closely monitoring their work to imbibe quality, maintain pace & exceed project goals

EBB & RTL Design

• Designed ROM modules (EBB & RTL) which are instruction memories accessed by control and sequencer units
• Designed RTL for clock generation counter logic
• Maintained CFBYTE module (EBB), a custom logic block for counting the total number of fails in a write operation
• Performed timing analysis with HSPICE simulations & LIBERATE tool

Firmware Design

• Developed Firmware for 5 generations of 3D-NAND Flash Memory, including first TLC (3-bits per cell), first QLC (4- bits per cell) & first PLC (5-bit per cell) technologies
• Designed performance improvement algorithms & features which improved sequential write performance by 60% and random write performance by 35%
• Designed "Dynamic-SLC" caching methodology, "Floating-Gate Sensing” methodologies & “Power-Loss-Algorithms” which improve the write performance, power efficiency and die-size (reduced capacitance)

Pre-Silicon Verification

• Responsible for full cycle of pre-silicon verification: (for 3 generations of 3-D NAND): test plan development, test bench coding, verifying functionality (or debugging) through waveforms (Verdi), automating checkers through System Verilog Assertions (SVAs), Regression Debug, and Coverage analysis

Post-Silicon Characterization

• Ran Silicon experiments (pathfinding for new features) to evaluate the performance and endurance impacts (MAGEV, MAGSV, Micro probe platforms)
• Worked with SSD, SDV & CBT platforms for path-finding & critical debug
• Worked in collaboration with Product Engineers, ASIC Engineers, Core & Analog Engineers for pathfinding,
  optimization, Silicon characterization & critical debug
• Performed Silicon vs Simulation correlation experiments to bridge the gap between Silicon & pre-silicon models

• Pre-Silicon validation of 3D NAND Memory design by using System Verilog Assertions & test benches