PRASANNAKUMAR SEERAM

Responsible for new product development, helping lead and drive programs involving latest M1 series of chipsets enabling next generation state-of-the-art consumer products.

• Expanded cross-functional organizational capacity by collaborating across departments(Design, Technology, System Hardware and Software) on priorities, functions and common goals to enable integration of custom built silicon into latest consumer products.
• Drove new process to align software, embedded system portables development schedules to align with SoC schedules, resulting in high quality silicon validation and Tape outs
• Led the effort with engineering teams to develop a customized process to identify hardware performance issues per platform during System level hardware and Software Validation, helping expedite bug fixes and stability of Silicon.
• Responsible for program status and risk to Executive Management.

Senior Technical program manager, in cloud server hardware development and validation team. Responsible for driving product specifications, cost, schedule, budgeting and managing cross-functional team responsible for system hardware development, validation and debug. Responsible for selecting and managing multiple design and manufacturing vendor partners

• Responsible for SOW, RFI and qualifying more than 5 vendors / suppliers to maintain fault tolerant supply channels.
• Drove multiple product marketing requirements with internal teams, prioritizing business critical deliverables with System design , HW/SW architecture teams to achieve the most cost efficient and reliable systems.
• Led the launch of the productizing the best in class Block storage server system

Engineering manager for cross-functional silicon validation team responsible for full product cycle from NPI to end of life. Projects include portfolio of mobile SOC chips and embedded systems in 10nm and 7nm silicon nodes powering latest consumer electronics.

• Responsible for developing test techniques to identify latent silicon defects with time delay fault and advanced voltage stress techniques, resulting in screening outgoing field failures of close to 150 DPPM.
• Led effort in improving customer experience working directly with key OEM's to detect failures in system environment by developing corners case control run methodology which helped develop production screens before volume ramps, achieving less than 250 defects(DPPM) at launch on latest technology nodes.
• Developed centralized silicon debug dash board, leveraging learning across SOC platforms, improving outgoing quality and time to market of follow on SOC.
• Responsible for building silicon models using key process control monitors(PCM) for predicting system bench mark performance(Geek bench/Dhrystone) at wafer level, helping optimize yield and performance curves at NPI.
• Lead engineer for qualifying and characterizing IP across multiple Fab houses for performance, yield and manufacturability.
• Responsible for reporting project status to executive management and core teams

• Lead Engineer responsible for end to end post silicon validation and characterization.
• Responsible for production enablement of power compensation IPs using Dynamic and Adaptive voltage schemes(DCVS/AVS).
• Led effort in developing predictive models for Days of use(DOU) and battery power in mass production, contributing to 20% reduction in DOU variation.
• Established advanced test and data techniques using spatial analysis like ZPAT and NNR to reduce customer level defects(DPPM) and improve product yields in Finfet technology.
• Patented work on test enhancement to deduct early life low voltage failures, improving unit cost by 5%

• Lead product engineer on industry's first 28nm SOC.
• Responsible for test plan development and production test program deployment.
• Developed new DOE process to reduce number of corner validated to optimize post silicon validation time by more than 30%.
• Partnered with reliability teams to optimize Qualification process reducing time to market by 15%.
• Improved production test time with predictive failure analysis at wafer level before package testing. Resulting 5% test cost reduction.