· Successfully led the PD team through Physical Implementation from library development to IP tape-out for multiple projects across 10nm, intel 7, intel 4 process nodes.
· Successfully led the standard cell library team through defining the standard cell library specification, library build, validation, and release process across 22nm, 14nm, 10nm, intel 7, intel 4, intel 3, intel 20A and intel 18A process nodes at business group level.
· A proven mentor of technical and soft skills for corporate behavior requirements.
· Visionary of high levels of automation and precise implementation of designs each time and every time.
· Always in the lookout of opportunities for achieving better Power, Performance and Area (PPA) improvements in all stages.
Accomplishments:
• Successfully led the PD team through Physical Implementation and tape-out for multiple projects across 10nm, intel 7, intel 4 process nodes.
• Automated handling of low power cells to create efficient secondary and tertiary power grid for better routing resources utilization and to avoid signal integrity issues.
• Defined and Developed utility to generate frequency-based RV cmax values for structural design construction to avoid signal integrity issues and improve the TAT of physical design execution cycle.
• Implemented debug flow and utilities for PD teams across the group. This reduced the debug time spent by PD engineers by 70% with improving the accuracy/quality of the debug
• Key point of contact for Design migration from one process node to other process nodes.
• Successfully led the standard cell library team through defining the standard cell library specification, library build, validation, and release process across 22nm, 14nm, 10nm, intel 7, intel 4, intel 3, intel 20A and intel 18A process nodes at business group level
• Key architect in planning and executing the automation of standard cell library build and validation and release process with zero quality issues
• Established utility to determine highly used standard cells across all the blocks in Mixed Signal IPs.
• Pioneered the distance table (AOCM/POCVM) generation utility and integrated it into the mainstream libraries with numerous automations.
Key Deliverables:
• Successfully led the PD team through Physical Implementation for Tiger Lake(10nm), Alder Lake (intel 7), Meteor Lake (intel 4) and Granite Rapids (intel 4) projects and responsible for all aspects of Physical Design for IP blocks covering synthesis, Floor planning, Clock Tree analysis, Placement, Clock tree synthesis, Placement optimizations, Routing, Timing and SI analysis/closure, ECO tasks (both timing and functional), EM/IR, DRC, LVS, ERC analysis & fixes, Low Power solution development & implementation
• All milestones released with 100% quality and within timelines
• Correct by Construction Timing and Physical verification convergences with semi-automated design recipes for floorplan, placement, clock tree synthesis, route, and fill.
• Key consultant of Tool Flow Methodologies for all IPs taped out by the business unit. Helped various PD teams debug/complete tape-out by guiding them with TFM, standard cell usage, Signal Integrity, Timing, DRC and LVS convergence.
• Key POC for aligning the library developments and releases with short term and long-term goals of the business unit.
• Pivotal player in conceiving, planning, and implementing the End-to-End library QA process automation for 100+ quality checks. This effectively saved 2 weeks per every library release.
• Condensed the IP design cycle time by 30% with quick turnaround for any issue and by fixing all the issues up front.
• Mentored and guided design teams and support teams both technically and in soft skills, ensuring all were trained in product knowledge and capable of performing assigned duties well. This elevated the quality of whole team in terms of their performance and interactions with peer team.
• Created a smaller set of standard cell library based on standard cell usage across Mixed signal IPs which almost 60% smaller than original cell count. P
Platform / Technology: 22nm,14nm,10nm, intel 7, intel 4, intel 3, intel20A, intel18A
Tool Suite: Synopsys Design Compiler, Synopsys IC-Compiler II, Fusion Compiler, Library Compiler, Conformal LEC-LP and LEC, Redhawk RV, Star RC Extraction, Primetime and ICV
• Drove multiple efficiency and methodology improvements across multiple domains to increase the productivity and reduce the TAT
INDUSTRIAL AWARD:
· Received 84 Departmental Impact Awards and recognition awards for helping other employees across the organization and quality IP drops within timelines and developed multiple quality checks and automation flows which improved the productivity, quality and TAT of IP execution cycle.
ACADEMIC EXCELLENCE:
· University Second rank in M. Tech Microelectronics
· Secured All India 1st Rank in written exam of Scientist/Engineer-SC [Electronics] -ISRO
· Secured All India 1st Rank in Masters Entrance Examination conducted by Manipal University
· Secured All India 23rd Rank in Masters Entrance Examination conducted by VIT University
· Secured 99.12 percentile in GATE Exam
· Secured State 4th Rank (460/470) in Intermediate First year conducted by Board of Intermediate Education, Andhra Pradesh in May 2005
· Awarded with Gold Medal and Pratibha award in 10th Class for securing state 12th rank (571/600) from Government of Andhra Pradesh.
· As a Team Captain we awarded with First Place in Kho-Kho, Cricket, Football and 4x100 Mtrs Relay in Zonal games conducted by Chittoor District Secondary School Athletic Association, A.P in Dec-2003.
· Got Individual Championship for First place in 100mtrs, 200mtrs, 400mtrs and 4x100 Mtrs Relay in Zonal games conducted by Chittoor District Secondary School Athletic Association, A.P in Nov-2002.