Praveen Kumar Adapala
Okemos,MI
Summary
Senior Analog IC Layout Designer with over 7 years of experience in high-performance analog/mixed-signal CMOS layout. Demonstrated expertise in custom physical layout and verification of circuits using Cadence Virtuoso XL in FinFET technologies. Seeking to leverage experience in top-level planning, floorplan for critical blocks, leading a team and developing IP level tape outs to drive design excellence.
Overview
7
7
years of professional experience
Work History
Senior Layout Design Engineer
Qualcomm India Pvt.Ltd
07.2017 - 01.2023
- I collaborated with the MSIP team to design several high-speed DAC IPs, including WLANDAC, TXDAC, and ETDAC across multiple FinFET technologies
- My responsibilities include aiding the ADC, PLL, and SERDES teams in block layout development
- Expertise in DAC top level and sub-level hierarchies (CAL DAC array, MSB array, LSB array, RLOAD, BIAS and CAL blocks)
- Responsible for DAC IP deliveries on time with low noise, low parasitic, best quality, and high efficiency
- Highly skilled in Floor Planning, Placement, Area Estimation, Signal & Power Routing of Macro Blocks, Full IP Integration and Chip Level
- Demonstrated leadership in managing multiple custom IC layout projects, collaborating closely with design engineers at Qualcomm SD team to ensure optimal circuit performance
- Recognized for the ability to work effectively both as part of a team and independently, providing valuable input, guidance, and task delegation to layout resources
- Skilled in fostering clear communication within multi-site team environments across different time zones.
Layout Design Engineer
Wafer Space Semiconductors Pvt.Ltd
12.2015 - 10.2021
- Worked alongside IT ODC projects for 1.5 years to finalize custom physical layouts and verify high-performance circuits
- Has a thorough grasp of Parasitic (R & C), Color Decomposition, Guard Rings, Isolation Techniques, Custom Fill vs Auto Fill, FINCODE, Matching Layers, IR Drop, Electromigration, Shielding, and Decaps
- I possess expertise in diverse matching techniques, covering differential pairs, current mirrors, resistors, capacitors, and BJT's matching
- Additionally, I am well-versed in layout-dependent effects such as LOD, WPE, OSE, CPO, and PPE
- I mentored junior team members in deploying IC layout techniques ensuring compliance with DRC and LVS standards, while also emphasizing best practices in floor planning and power & signal routing.
Education
Master of Science - Master of Science in Engineering Management
Trine University
Angola, IN05.2024
Master of Science - DIGITAL ELECTRONICS & COMMUNICATION ENGINEERING
Jawaharlal Nehru Technological University
Hyderabad, India01.2015
Bachelor of Science - Electronics & Communications Engineering
Jawaharlal Nehru Technological University
Hyderabad, India03.2012
Skills
- Analog IC Layout Design
- Cadence Virtuoso Layout Editor
- Floorplan, Placement, Routing, Top level checks
- Physical Verifications- LVS, DRC, ERC, EMIR
Additional Information
- FINFET: TSMC (N3E, N6RF, N7P, N28, N28RF)
Samsung (5LPE, 11LPP, 14LPCRF, 14LPPRF)
Global Foundries(14nm)
- FDSOI: Global Foundries (22FDSOI)
- CMOS: TSMC 28nm, N40nm, N45nm
EDA EXPERTISE
- Cadence Virtuoso L, XL & EXL
- Cadence Virtuoso Schematic Editor
- Mentor Graphics Calibre LVS, DRC, ERC
- Verification Synopsis, Calibre & PVS
Timeline
Senior Layout Design Engineer
Qualcomm India Pvt.Ltd
07.2017 - 01.2023
Layout Design Engineer
Wafer Space Semiconductors Pvt.Ltd
12.2015 - 10.2021
Master of Science - Master of Science in Engineering Management
Trine University
Master of Science - DIGITAL ELECTRONICS & COMMUNICATION ENGINEERING
Jawaharlal Nehru Technological University
Bachelor of Science - Electronics & Communications Engineering
Jawaharlal Nehru Technological University
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