Praveenkumar Thankappan

Rich and varied 18 years of experience in pre-silicon verification with ownership and execution in IP(block), Subsystem and SoC verification with extensive exposure to AMBA based protocols and designs, PCIe, USB, Ethernet and MIPI protocols

IP/Subsystem Verification

1. Verification of Power and Clock control subsystem for Mobile chipset

• The design consists of two ARM processors; Cortex M0P(Booting) and Cortex M3, Power management engine and clock control blocks.
• The project involved the testbench and testcase development, power aware simulation, debugging and functional coverage implementation.

2. Verification FEC Accelerator for a 5G Modem

• The responsibility in this project was the functional verification of sub blocks like FRAM Arbiter, Circular Buffer Manager, AXI Master/Slave and Encoder/Decoder
• Verification environment was in UVM methodology.
• Lead a team of 7 engineers.

3. Verification of Content Processing Module (CPM) IP

• The CPM is an IP consisting of the hardware accelerators (encryption, authentication, compression) with PCIe and Ethernet endpoints.
• Developed testbench and testcases in UVM.
• Lead a team of 12 engineers.

4. Design, Verification, and implementation of HDMI 2.1 Transceiver

• The HDMI 2.1 transceiver had HDMI Rx, HDMI Tx and Video Processing submodules.
• Handled UVM based module and chip top level verification of HDMI Tx and the Video Processing blocks in UVM.
• Lead a team of 6 engineers.

5. Verification of the MIPI DSI subsystem

• The subsystem has a MIPI Receiver and a D-PHY
• Verification environment was in UVM methodology.

6. Verification of MIPI CSI-2/DSI Receiver IP

• This project is the module level verification of the MIPI CSI-2 and DSI protocol Receiver IP
• Developed the verification environment in UVM methodology.
• Lead a team of 6 engineers.

7. Verification of SDRAM Controller

• This is the verification of a memory controller of a 2GB SDRAM and the verification environment was in UVM.
• Developed testbench and testcases.

8. Verification of IOSF to OCP bridge - Intel Corporation

• OVM Based Functional Verification of IOSF2OCP Bridge IP
• Developed testcases and implemented the RAL.

9. AVM based Functional and Gate level Verification of DDRPHY Architecture - Intel Corporation

• Involved in Verification component development and functional coverage.
• Handled the Gate level simulation.

SoC and System Level Verification

1. SoC and Subsystem Level Verification of RISC-V based SoC for Data Analytics

• The SOC had two RISC-V cores (Main and Bootstrap System) and PCIe Gen4, 100G Ethernet, LPDDR5 memory subsystems.
• Responsible for PCIe, Ethernet and LPDDR5 memory subsystems, Tile link network and chip top verification
• Lead the team at onsite/offshore and involved in chip top and subsystem level testbench development, verification planning and tracking.

2. SoC, System Level and Power Aware Verification of Cortex-M3 based SoCs for Modular phone project - Toshiba Semiconductor Japan

• The SOC had a local Cortex-M3 processor which controlled the Peripheral IP like MIPICSI2, MPI-CSI3, MIPI-DSI, MIPI-UNIPRO, I2S, HSIC(USB), SDIO, DMA Controller
• Responsible for UVM based System Level verification involved the verification of Unipro L3 level switching for Unipro data Packets driven between the various bridge-SOCs connected via a Unipro Switch, MIPI CSI2-DSI subsystem verification and Power Aware Simulation
• Lead the team at onsite/offshore.

3. Verification of SoC for High-speed communication - Toshiba Semiconductor

• This project includes the functional verification of Ethernet, PCIe subsystems and the SoC connecting both.
• Responsibilities included the design of testbench architecture for the SoC, test plan development and lead the team of 4 members for SoC verification.

4. Verification of the MPU subsystem for automobile applications - Renesas Electronics Japan

• This project is the SoC level verification of the RH850 processor based MCU for dashboard control in high end automobiles.
• Used Verilog and assembly language for testbench and testcases.
• Lead a team of 7 engineers.

5. Verification of the RH850 processor based MCU for automobile applications - Renesas Electronics Japan

• This project is the SoC level verification of the RH850 processor based MCU for body control in high end automobiles.

6. Verification of a PowerPC based SoC for Small and Medium Business applications - Freescale Semiconductor

• SoC included USB, PCI, Ethernet Controller, SATA etc.
• Developed and simulated of test cases in Vera and PowerPC assembly for the PowerPC core.

7. Verification of a PowerPC based SoC for Small Office Home Office applications - Freescale Semiconductor

• Developed testcases in VERA and Assembly Language and simulation for Power PC core complex which includes a PowerPC processor and cache.

8. Verification of a PowerPC based SoC for Small Office Home Office applications - Freescale Semiconductor

• Developed testcases in VERA and Assembly Language and simulation for Power PC core complex which includes a PowerPC processor and cache.